4 of 4 Contract Adaptive Web Design Jobs in the UK

Senior IP Design Engineer – Contract – Remote (UK) We are recruiting an experienced Senior IP Design Engineer to join a leading technology programme delivering next-generation FPGA and Adaptive SoC solutions. This is a remote UK contract offering the opportunity to work on high-performance digital … cutting-edge systems. As a Senior IP Design Engineer, you will design and implement SystemVerilog RTL, developing synthesis-ready IP targeting FPGA/Adaptive SoC platforms. You will own end-to-end design flow including RTL architecture, integration, timing closure, place-and-route (P&R), constraints ...

recruiting an experienced Senior IP Design Engineer to join a leading technology programme delivering next-generation FPGA and Adaptive SoC solutions. This is a remote UK contract offering the opportunity to work on high-performance digital IP for cutting-edge systems. As a Senior IP Design Engineer … will design and implement SystemVerilog RTL , developing synthesis-ready IP targeting FPGA/Adaptive SoC platforms. You will own end-to-end design flow including RTL architecture, integration, timing closure, place-and-route (P&R), constraints and optimisation . The role focuses on high-speed digital interfaces ...

Title: Senior IP Design Engineer Location: Belfast, UK (Remote) Job Type: Contract (Inside IR35) Duration: 6 months, with the potential for extension based on project needs and performance Job Summary: Join Tata Consultancy Services (TCS) as a Senior IP Design Engineer and play a key role in designing … high-performance IP for next-generation FPGA/Adaptive SoC technologies. Work remotely on impactful projects that help shape the future of FPGA and SoC design, collaborating with top-tier engineering teams and expanding your technical horizons. About the Company: TCS is a leading transformation company partnering with ...

Responsibilities: Research and develop next-generation data prefetching techniques including ML-based predictors and irregular access pattern prediction. Design advanced speculative execution mechanisms and thread-level speculation (TLS). Research branch prediction innovations including neural branch predictors, path-based prediction, slice-based prediction, and conditional control flow slice techniques. … Design ISA extensions and microarchitectural support for compiler-directed optimizations including software pipelining and instruction scheduling hints. Propose microarchitectural support for JIT compilation, dynamic optimization, and adaptive execution. Design simulation and prototyping frameworks integrating compiler toolchains with architectural models for microarchitectural evaluation. Participate in joint research projects ...