Firmware requirements and architecture from system requirements A structured approach to firmware design (RTCA DO-254 or similar) Experience required: FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Cryptography and anti-tamper techniques Electronics test methods and equipment HNC/HND or More ❯
digital systems that meet challenging future customer requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Auto-generated code using model driven engineering using Matlab and Simulink tools Derivation of More ❯
skills Experience of developing FPGA using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools, including HDL Designer, ModelSim/Questa, and Precision Familiarity with Xilinx/Intel (Altera)/Microsemi (Actel) design flows and third-party synthesis tools Experience in specifying timing and area constraints for efficient FPGA place and route Independent verification using VHDL Experience of More ❯
skills Experience of developing FPGA using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools, including HDL Designer, ModelSim/Questa, and Precision Familiarity with Xilinx/Intel (Altera)/Microsemi (Actel) design flows and third-party synthesis tools Experience in specifying timing and area constraints for efficient FPGA place and route Independent verification using VHDL Experience of More ❯
Cambridge, Cambridgeshire, England, United Kingdom
MicroTECH Global Ltd
VHDL Translate novel functional computing models into optimised RTL architectures Implement high-throughput, pipelined digital logic and memory interfaces Contribute to simulation, synthesis, debug, and validation of designs on Altera Agilex FPGAs and/or AMD Xilinx Versal Collaborate on architectural evaluation of latency, power, and scalability Write clean, maintainable RTL and contribute to documentation, DFT/DFM, and … SystemVerilog and/or VHDL Tech Stack: Quartus Prime Pro, Vivado, ModelSim, QuestaVerilog, SystemVerilogC, C++, Python, Haskell, Erlang, TCLGit, Jira Desirables:PCI3 Gen 6 experience Experience with Intel/Altera Agilex 5E FPGAsVHDLExposure to compute-in-memory, functional or dataflow architectures UVM or equivalent verification experience More ❯
