16 of 16 Contract PCIe Jobs in the UK excluding London

Xilinx, TCL, Verilog, SystemVerilog, and UVM Experience with FPGA architectures including Xilinx 7 Series, UltraScale, Intel (Altera), or Microsemi (Actel) High-speed interfaces: PCIe, Ethernet, JESD Model-driven engineering and auto-generated code (MATLAB/Simulink) Structured firmware development approaches (eg RTCA DO-254 or similar) Knowledge of cryptography ...

similar) Experience required: FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Cryptography and anti-tamper techniques Electronics test methods and equipment HNC/HND or Undergraduate Degree (Electronic Engineering, Computer Science, AI, Games ...

Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Auto-generated code using model driven engineering using Matlab and Simulink tools Derivation of detailed Firmware requirements and architecture from ...

Skills and Experience required Strong experience with UVM, constrained-random verification and coverage-driven verification sign-off. Hands-on verification experience with 100Gb Ethernet, PCIe Gen5, and AMBA/AXI protocols. Some proficiency in Python Scripting for automation and regression management within CI/CD environments. Experience with adaptive ...

Perform functional validation of a new SoC designed with high-end ARM processors. Execute functional bring-up of SoC interfaces such as LPDDR, Ethernet, PCIe, HBM, CPUs, Low-Speed IOs (UART, I2C, I3C, SPI), and Coherent Mesh. Develop bare-metal C tests and debug using FPGA HAPS/Zebu emulation ...

level verification and debug activities What were looking for Strong hands-on experience with UVM and constrained-random verification Knowledge of 100Gb Ethernet, PCIe Gen5, AMBA/AXI Python scripting and CI/CD-based regression workflows Solid Git experience Familiarity with Adaptive SoC design flows ( Vivado/Vitis ) Understanding ...

solid understanding of SoC architectures, memory interfaces, and platform design in embedded compute or related fields. Proven experience with high-speed interface standards (e.g., PCIe Gen5/6, LPDDR5/6) and associated peripherals. Hands-on experience with embedded system board design, including complex LSI devices such as FPGAs, embedded ...

experience with SoC architectures, memory interfaces, and platforms involving embedded compute or AI. High-Speed Interconnects: Hands-on experience with cutting-edge standards, specifically PCIe Gen5/6 and LPDDR5/6 . Complex Board Design: Proven competence in designing boards with high-complexity LSI devices (FPGAs), embedded firmware ...

architecture, integration, timing closure, place-and-route (P&R), constraints and optimisation. The role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows. Key Responsibilities Design high-performance … using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting timing, P&R and integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocks Drive timing closure using Vivado toolchains Develop automation using Python/Tcl scripting Collaborate with hardware, SoC, firmware and integration ...

integration, timing closure, place-and-route (P&R), constraints and optimisation . The role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA , and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows . Key Responsibilities Design high-performance … using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting timing, P&R and integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocks Drive timing closure using Vivado toolchains Develop automation using Python/Tcl scripting Collaborate with hardware, SoC, firmware and integration ...

RTOS. You’ll contribute to board bring-up, hardware/software co-debug, system verification, driver-level development, and support high-speed interfaces including PCIe and 100GbE. Collaboration with global engineering teams is central to this role. Key Skills Required Embedded software development in C/C++, plus scripting with … Strong experience with bare-metal, Yocto Linux, Zephyr, RTOS SoC software flows, co-simulation, hardware debug and board bring-up High-speed interface experience: PCIe, Ethernet, 100GbE, SerDes Proficient with Git, CI/CD pipelines Advantageous: familiarity with AMD Adaptive SoC, Vivado, Vitis What’s on Offer Long-term programme ...

RTOS . Youll contribute to board bring-up, hardware/software co-debug, system verification, driver-level development , and support high-speed interfaces including PCIe and 100GbE . Collaboration with global engineering teams is central to this role. Key Skills Required Embedded software development in C/C++ , plus scripting … Strong experience with bare-metal , Yocto Linux , Zephyr , RTOS SoC software flows , co-simulation, hardware debug and board bring-up High-speed interface experience: PCIe , Ethernet , 100GbE , SerDes Proficient with Git , CI/CD pipelines Advantageous: familiarity with AMD Adaptive SoC , Vivado , Vitis Whats on Offer Long-term programme with ...

Perform functional validation of a new SoC designed with high-end ARM processors. Execute functional bring-up of SoC interfaces such as: LPDDR Ethernet PCIe HBM CPUs Low-Speed IOs (UART, I2C, I3C, SPI) Coherent Mesh Develop bare-metal C tests and debug using FPGA HAPS/Zebu emulation platforms … Verification teams Electrical Testing & Characterization teams Production Firmware teams Essential Skills Strong proficiency in Embedded C . Experience with high-speed protocols such as: PCIe Gen6 Die-to-die links LPDDR5 HBM3 Hands-on expertise with ARM high-end CPUs and ARM cache-coherent interconnect protocols . Proven validation experience ...

implement UVM/SystemVerilog verification environments Deliver constrained-random verification and achieve coverage sign-off Verify high-speed interfaces including Ethernet (100G) and PCIe (Gen4/Gen5) Integrate and use Verification IP (VIP) Develop and maintain Python-based regression and CI workflows Collaborate with design, architecture, and SoC teams Essential … Skills & Experience Strong experience as a Verification Engineer/Design Verification Engineer Expert knowledge of UVM and SystemVerilog Experience with Ethernet, PCIe, AMBA/AXI Proven ownership of test plans and coverage closure Python scripting and Git-based workflows Experience in ASIC, SoC, or IP verification environments Desirable Experience with ...

Perform functional validation of a new SoC designed with high-end ARM processors. Execute functional bring-up of SoC interfaces such as LPDDR, Ethernet, PCIe, HBM, CPUs, Low-Speed IOs (UART, I2C, I3C, SPI), and Coherent Mesh. Develop bare-metal C tests and debug using FPGA HAPS/Zebu emulation … Architects, RTL Verification, Electrical Testing & Characterization, and Production Firmware teams. Essential Skills Strong proficiency in Embedded C. Experience with high-speed protocols such as PCIe Gen6, die-to-die links, LPDDR5, and HBM3. Hands-on expertise with ARM high-end CPUs and ARM cache-coherent interconnect protocols. Proven validation experience ...

functional validation of next-generation SoC designs based on high-performance ARM processors. Lead functional bring-up of critical SoC interfaces, including LPDDR, Ethernet, PCIe, HBM, CPUs, low-speed peripherals (UART, I2C, I3C, SPI), and cache-coherent mesh interconnects. Create and debug bare-metal C test software using FPGA HAPS … Electrical Test & Characterization, and Production Firmware groups. Essential Skills Advanced proficiency in Embedded C development. Strong experience with high-speed interfaces and protocols, including PCIe Gen6, die-to-die links, LPDDR5, and HBM3. In-depth hands-on experience with high-end ARM CPUs and ARM cache-coherent interconnect technologies. Demonstrated ...