6 of 6 Contract SystemVerilog Jobs in the UK excluding London

ways of working across UK wide FPGA/Firmware delivery teams. Creating innovative VHDL based FPGA designs Advanced verification techniques using either VHDL or SystemVerilog/UVM Current FPGA technologies from either Xilinx, Altera or Microsemi and their tools Model Driven Engineering tools including MATLAB and Simulink High Speed Interface ...

software teams to deliver robust FPGA-based solutions for advanced electronic systems. Key Responsibilities Design and develop FPGA firmware using VHDL (Verilog/SystemVerilog desirable). Verify and debug firmware designs at module, hardware, and system level. Translate system and hardware requirements into detailed firmware requirements. Support integration, validation ...

working across UK wide FPGA/Firmware delivery teams. Key Skills : Creating innovative VHDL based FPGA designs Advanced verification techniques using either VHDL or SystemVerilog/UVM Current FPGA technologies from either Xilinx, Altera or Microsemi and their tools Model Driven Engineering tools including MATLAB and Simulink High Speed Interface ...

Principal Firmware Engineer Luton Paying up to £80p/h (Umbrella) Responsibilities : Artificial Intelligence, including machine learning and genetic algorithms Auto-generated code using model-driven engineering using MATLAB and Simulink tools Design tools such ...

Role: Senior IP Design Engineer Type: Contract Location: Belfast, UK Hybrid Job details: Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements. Key Skills: SystemVerilog RTL design 100Gb Ethernet, PCIe Gen5, AMBA/AXI Deep understanding ...

block- and system-level designs including RISC-V cores, cryptographic IP (OTBN), and key peripherals (USB, I2C, SPI). Key Responsibilities Develop and debug SystemVerilog/UVM testbenches Create verification plans, tests, and coverage Review contributions and resolve regressions Support CI/test infrastructure Collaborate with partners through tapeout Requirements … 5+ years industry verification experience Strong SystemVerilog and UVM Full verification lifecycle experience through tapeout C and/or Python for automation Git/GitHub collaboration Desirable: Formal verification (Jasper), RISC-V/ISA knowledge, security verification, silicon bring-up, or technical leadership experience. ...