7 of 7 Contract SystemVerilog Jobs in the UK excluding London

that are degree qualified (or equivalent) with significant experience in FPGA development. * Competent VHDL Language and Design Skills. * Competent Verification Skills using VHDL and SystemVerilog methodologies * A deep proven level of experience designing for Xilinx, Intel or Microsemi FPGAs * Experience of professionally configuring and documenting designs * Experience of working ...

that are degree qualified (or equivalent) with significant experience in FPGA development. Competent VHDL Language and Design Skills. Competent Verification Skills using VHDL and SystemVerilog methodologies A deep proven level of experience designing for Xilinx, Intel or Microsemi FPGAs Experience of professionally configuring and documenting designs Experience of working ...

that are degree qualified (or equivalent) with significant experience in FPGA development. Competent VHDL Language and Design Skills. Competent Verification Skills using VHDL and SystemVerilog methodologies A deep proven level of experience designing for Xilinx, Intel or Microsemi FPGAs Experience of professionally configuring and documenting designs Experience of working ...

About this Position: We are seeking an experienced Senior/Principal FPGA Engineer to join a dynamic team working on cutting-edge systems within the aerospace and defence industry. This role focuses on designing and ...

opportunity to work on high-performance digital IP for cutting-edge systems. As a Senior IP Design Engineer, you will design and implement SystemVerilog RTL, developing synthesis-ready IP targeting FPGA/Adaptive SoC platforms. You will own end-to-end design flow including RTL architecture, integration, timing closure, place …/AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows. Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting timing, P&R and integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/ ...

opportunity to work on high-performance digital IP for cutting-edge systems. As a Senior IP Design Engineer, you will design and implement SystemVerilog RTL , developing synthesis-ready IP targeting FPGA/Adaptive SoC platforms. You will own end-to-end design flow including RTL architecture, integration, timing closure, place … AMBA , and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows . Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting timing, P&R and integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/ ...

designs, owning test plans, driving coverage closure, and supporting integration using industry-standard verification environments. Key Responsibilities Design and implement UVM/SystemVerilog verification environments Deliver constrained-random verification and achieve coverage sign-off Verify high-speed interfaces including Ethernet (100G) and PCIe (Gen4/Gen5) Integrate and use Verification … with design, architecture, and SoC teams Essential Skills & Experience Strong experience as a Verification Engineer/Design Verification Engineer Expert knowledge of UVM and SystemVerilog Experience with Ethernet, PCIe, AMBA/AXI Proven ownership of test plans and coverage closure Python scripting and Git-based workflows Experience in ASIC ...