4 of 4 Contract Tcl Jobs

Satellite Electrical Engineer

Hiring Organisation
Yolk Recruitment Limited
Location
Stevenage, Hertfordshire, South East, United Kingdom
Employment Type
Contract
Contract Rate
£40 - £45 per hour
languages, in particularly writing and debugging Linux/Unix bash scripts is an advantage. Knowledge of a programming language such as C, Java, python, TCL ...

Senior IP Design Engineer

Hiring Organisation
Stackstudio Digital Ltd
Location
United Kingdom
Employment Type
Contract, Work From Home
Contract Rate
From £400 to £450 per day
/Adaptive SoC design flow, including place & route (P&R) and timing closure Proficiency in Vivado/Vitis Strong scripting skills in Python and Tcl Experience with Git and CI/CD Additional Information: Remote role: No regular office attendance required. ...

Senior IP Design Engineer

Hiring Organisation
DCV Technologies
Location
Belfast, City of Belfast, County Antrim, United Kingdom
Employment Type
Contract
Contract Rate
£35 - £60/hour
role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows. Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting … integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocks Drive timing closure using Vivado toolchains Develop automation using Python/Tcl scripting Collaborate with hardware, SoC, firmware and integration teams Essential Skills Strong SystemVerilog RTL design experience FPGA/Adaptive SoC design flow: synthesis ...

Senior IP Design Engineer Contract Remote (UK)

Hiring Organisation
DCV Technologies Limited
Location
Belfast, County Antrim, Northern Ireland, United Kingdom
Employment Type
Contract, Work From Home
Contract Rate
From £35 to £60 per hour
role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA , and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows . Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready … integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocks Drive timing closure using Vivado toolchains Develop automation using Python/Tcl scripting Collaborate with hardware, SoC, firmware and integration teams Essential Skills Strong SystemVerilog RTL design experience FPGA/Adaptive SoC design flow: synthesis ...