Saffron Walden, England, United Kingdom Hybrid / WFH Options
Vantage Consulting
/O in FPGA. * Understanding of the design of high-speed digital circuits for real-time systems. * Experience of design verification by both simulation (SystemVerilog or similar) and hardware testing. * Experience of software design using C/C++, Python, or Rust. * Proficient using test equipment such as oscilloscopes, spectrum analysers more »
Great Chesterford, England, United Kingdom Hybrid / WFH Options
Vantage Consulting
/O in FPGA. Understanding of the design of high-speed digital circuits for real-time systems. Experience of design verification by both simulation (SystemVerilog or similar) and hardware testing. Experience of software design using C/C++, Python, or Rust. Proficient using test equipment such as oscilloscopes, spectrum analysers more »
great chesterford, east anglia, United Kingdom Hybrid / WFH Options
Vantage Consulting
/O in FPGA. Understanding of the design of high-speed digital circuits for real-time systems. Experience of design verification by both simulation (SystemVerilog or similar) and hardware testing. Experience of software design using C/C++, Python, or Rust. Proficient using test equipment such as oscilloscopes, spectrum analysers more »
Data processing Cryptographic algorithms and side-channel attacks High performance CPU architecture and design. Modern SoC design methodologies and architecture Tools/Technologies Verilog, SystemVerilog, Perl Shell scripting, Python, Sage, Tcl C, C++ MATLAB, Xilinx Vivado Unix, Linux Front-end ASIC design tools - synopsys/cadence/mentorExcellent salary, bonus more »
driver development Comprehensive understanding of clock domain crossing techniques Strong knowledge of FPGA tool flows (synthesis, partitioning, place&route, timing analysis) Excellent skills in SystemVerilog/Verilog/VHDL Experience in scripting (tcl preferable) and Python programming Experience using Questa, ModelSim, GHDL, Verilator, cocotb Experience using Quartus/Vivado/ more »
such as shell scripting and basic Perl scripts Ability to work with technical writers in the production of technical documentation. Tools/Technologies Verilog, SystemVerilog, Perl Shell scripting, Python, Sage, Tcl C, C++ MATLAB, Xilinx Vivado Unix, Linux Front-end ASIC design tools - synopsys/cadence/mentor Excellent salary more »
flow. This includes: Working closely with the RTL design team to develop comprehensive verification strategies Creating and reviewing design verification documentation Designing and implementing SystemVerilog/UVM based verification IP and testbenches Improving existing testbenches to increase performance, quality and efficiency Testing and debugging Verilog RTL Defining and implementing functional more »
flow. This includes: Working closely with the RTL design team to develop comprehensive verification strategies Creating and reviewing design verification documentation Designing and implementing SystemVerilog/UVM based verification IP and testbenches Improving existing testbenches to increase performance, quality and efficiency Testing and debugging Verilog RTL Defining and implementing functional more »
embedded C/C++ based SoC verification environments Knowledge of assembly language (preferably ARM), C/C++ and/or hardware verification languages e.g. (SystemVerilog), shell programming/scripting (g. Tcl, Perl, Python etc.) Experienced in one or more of various verification methodologies – UVM, formal, low power, emulation Exposure to more »
embedded C/C++ based SoC verification environments Knowledge of assembly language (preferably ARM), C/C++ and/or hardware verification languages e.g. (SystemVerilog), shell programming/scripting (g. Tcl, Perl, Python etc.) Experienced in one or more of various verification methodologies – UVM, formal, low power, emulation Exposure to more »
Cambridge, Cambridgeshire, East Anglia, United Kingdom
Langham Recruitment Limited
highly skilled, close-knit team. Key Responsibilities: Digital design development for custom IC Integration including the writing of IP design specifications, coding Verilog and SystemVerilog models for simulation, synthesis and static timing analysis and writing automated simulation and verification build scripts. Building automated pre-silicon verification environment whilst supporting early more »
embedded C/C++ based SoC verification environments Knowledge of assembly language (preferably ARM), C/C++ and/or hardware verification languages e.g. (SystemVerilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.) Experienced in one or more of various verification methodologies – UVM/OVM, formal, low power, emulation more »
working closely with a skilled and diverse team, and developing the environment. Must-have experience: Circa 5+ years' experience in FPGA development VHDL/SystemVerilog RTL design/coding Tcl/Python or similar coding/scripting (Nice-to-have experience): UVM verification embedded software/firmware DevOps/software more »
PhD in electrical engineering or computer science Minimum 5 years of experience in digital ASIC design Excellent programming skills in hardware description languages (e.g. SystemVerilog) Good programming skills in scripting languages (e.g. Python, Perl, Tcl) Expertise in verification methodologies & tools (e.g. UVM) would be a plus Excellent written and verbal more »
embedded C/C++ based SoC verification environments Knowledge of assembly language (preferably ARM), C/C++ and/or hardware verification languages e.g. (SystemVerilog), shell programming/scripting (g. Tcl, Perl, Python etc.) Experienced in one or more of various verification methodologies – UVM/OVM, formal, low power, emulation more »
Skills and Experience : Worked on embedded C/C++ based SoC verification environments Knowledge of assembly language (preferably ARM), and hardware verification languages e.g. (SystemVerilog), shell programming/scripting (g. Tcl, Perl, Python etc.) Experienced in one or more of various verification methodologies – UVM, formal, low power, emulation Exposure to more »
Implementing Regression tests Performing Formal Verification Working closely with IC designers and post-silicon engineers Qualifications and Background Requirements: Knowledge/experience with HDL (SystemVerilog/Verilog/VHDL), particularly for testbenches creation Knowledge/experience in scripting languages, such as Tcl and Python Some knowledge of ASIC design flow more »
help develop digital designs for custom IC integration and design and validate new silicon designs. Experience: Experience in ASIC or FPGA Design Strong Verilog, SystemVerilog experience Python experience CPU architecture is a plus. You will be part of a company where the work environment is stimulating and exciting, as you more »
help develop digital designs for custom IC integration and design and validate new silicon designs. Experience: Experience in ASIC or FPGA Design Strong Verilog, SystemVerilog experience Python experience CPU architecture is a plus. You will be part of a company where the work environment is stimulating and exciting, as you more »
to enhancing Verification strategy and architecture of IP testbenches.Key Skills At least 8 years of experience in Verification working with Verilog and/or SystemVerilog; 5 years of experience on IP/block level Test-bench bring up on SV UVM based platform; The ability to understand complex design specification more »
to enhancing Verification strategy and architecture of IP testbenches.Key Skills At least 8 years of experience in Verification working with Verilog and/or SystemVerilog; 5 years of experience on IP/block level Test-bench bring up on SV UVM based platform; The ability to understand complex design specification more »
Cambridge, England, United Kingdom Hybrid / WFH Options
Codasip
of own work YOU SHOULD HAVE: Over 5 years recent and relevant module design experience within at least one HDL (VHDL/Verilog/SystemVerilog) Knowledge of computer systems and architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning more »
cambridge, east anglia, United Kingdom Hybrid / WFH Options
Codasip
of own work YOU SHOULD HAVE: Over 5 years recent and relevant module design experience within at least one HDL (VHDL/Verilog/SystemVerilog) Knowledge of computer systems and architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning more »
years of experience in ASIC development Expertise in verification methodologies & tools Strong knowledge of UVM Excellent programming skills in hardware description languages (e.g. SystemVerilog) Good programming skills in scripting languages (e.g. Python, Perl, Tcl) Excellent written and verbal communication skills in English For more information and to apply, please contact more »
today and in the future. Requirements: A BSc/MSc degree in Computer Engineering or similar Proven project experience of verification Strong experience in SystemVerilog or Verilog testbench creation Experience with OVM, VMM, UVM methodologies Effective problem solving, communication and team working skills (essential!)This position offers the opportunity to more »
