126 to 150 of 242 Permanent SystemVerilog Jobs

determine implementation approaches, and design testbenches. Expertise in root‐cause analysis of complex issues, with the ability to resolve them efficiently. Deep knowledge of SystemVerilog and UVM. Capability to develop and enhance verification flows. Familiarity with ASIC design methodologies, flows, and tools. Proficiency in planning, estimating, and tracking personal tasks. ...

analytical skills Professional experience (2+ years) in RTL functional verification for FPGA or ASICExperience with code and functional coverage collection/analysisExperience with SystemVerilog and industry-standard frameworks such as UVMExperience with PythonComfortable in a Linux environmentFamiliarity with Verilator and/or Cocotb preferredC++ experience is a plusA bachelor ...

/emulation mismatches and test failures. Hands-on experience with emulation platforms such as ZeBu, Palladium, or Strato. Familiarity with RTL languages such as SystemVerilog/Verilog Experience in collaboration with EDA vendors to introduce new capabilities, resolve tool issues, and contribute to future tool improvements. Skilled in planning system ...

with Systems, Hardware and Software teams. Key Responsibilities Design and develop robust VHDL-based FPGA solutions Verify FPGA designs using VHDL and/or SystemVerilog Work closely with Systems, Hardware and Software teams on integration Analyse system/hardware requirements and derive detailed FPGA requirements Debug FPGA designs and support … work across multidisciplinary engineering teams Real-time, embedded or safety-critical FPGA development Experience with RTCA/DO-254 DAL A or DAL B SystemVerilog/UVM verification Aerospace or Defence experience Embedded processor cores such as ARM within FPGA designs Knowledge of modern FPGA device families Experience working within ...

Job Description:Salary: 60,000 to 84,955Leonardo UK operates a grade-based salary framework with broad bands. The salary range shown reflects the approved grade band for this role, or a narrower hiring range ...

Job Description: Your impact An exciting opportunity has arisen within Leonardo for a Lead Firmware/FPGA Specialist to work within the Surveillance Sector, developing firmware, working on FPGAs, that underpins both our current proven ...

Digital Verification Engineer to verify complex digital hardware architectures and contribute across the full verification lifecycle. You will design verification plans, implement testbenches with SystemVerilog/UVM, and apply constrained random verification, coverage-driven techniques, and SVA checks. Collaboration across automotive, microcontroller, and connectivity domains is expected. #J-18808-Ljbffr ...

test complex IPs such as Crypto Accelerators and PCIe controllers, ensuring they function with software and other subsystems. You will write test plans, develop SystemVerilog testbenches, and collaborate with cross-functional teams to deliver robust IPs for diverse market sectors. #J-18808-Ljbffr ...

compute teams in Cambridge and Bristol. You will verify complex ASIC/processor designs, develop verification plans, and drive coverage to closure using SystemVerilog, UVM, SVA, and Python. Join a team at the forefront of AI compute and processor technology with flexible working and a strong compensation package ...

will build verification environments, write test plans, diagnose issues, and drive coverage closure across power, security and performance. A background in UVM/SystemVerilog or formal verification and a passion for open source are #J-18808-Ljbffr ...

will develop RTL, SDC/UPF constraints, integrate IPs and work with verification and implementation teams to ensure high‐quality designs. The role requires SystemVerilog/Verilog HDL skills, strong RTL design grounding, UNIX scripting, and collaboration across CPU, GPU, multimedia IP. #J-18808-Ljbffr ...

Technologies International Ltd in Cambridge seeks an ASIC verification specialist with hands-on FPV experience to advance GPU RTL verification pipelines. You will write SystemVerilog assertions, develop formal testbenches, and collaborate with global teams to achieve formal sign-off using JasperGold and related tools. Qualifications include a Bachelor’s degree ...

complex IPs such as Crypto Accelerators, HW DVFS components, PCIe controllers, and interconnect fabrics, ensuring integration with software. You will write test plans, develop SystemVerilog testbenches and C-based tests, debug failures and collaborate across multiple engineering teams to enable robust, high-quality silicon solutions. #J-18808-Ljbffr ...

ASIC Verification Engineer specializing in Formal Property Verification (FPV) to join the Engineering Group > ASICS Engineering. You will develop FPV test plans, write SystemVerilog Assertions, and collaborate with global RTL design and DV teams to drive sign-off. The role requires 2+ years in ASIC design/verification, a degree ...

London. The role involves delivering emulation capabilities for GPU designs while collaborating with design and software teams. Candidates should have strong knowledge in SystemVerilog, debugging skills, and proficiency in programming languages such as Python, C, and C++. The position offers the opportunity to innovate and be part of a dynamic ...

complex, large-scale GPU projects. This role involves micro-architecture development, logic synthesis, and debugging of design issues. Ideal candidates will have experience with SystemVerilog, VHDL, and strong problem-solving skills. The team values diverse perspectives, promoting an inclusive work environment. Join us to influence the design flow of cutting ...

verification for complex CPUs and CHERI-enabled technologies within UK design centres in Cambridge or Bristol. Ideal candidates have hands-on experience with SystemVerilog, Python, C++, and Rust, plus Linux automation, and a solid understanding of CPU architectures. #J-18808-Ljbffr ...

algorithm modelling to RTL sign-off and silicon bring-up. You will collaborate with digital design, optics, and software teams, develop verification environments with SystemVerilog/UVM, constrained-random testing, and formal methods, and contribute to reusable verification methodologies while mentoring junior engineers. #J-18808-Ljbffr ...

will develop UVM testbenches, lead verification activities, and ensure project closure through metrics tracking. The ideal candidate will demonstrate strong expertise in verification methodologies, SystemVerilog, and communication skills to collaborate effectively across teams. By joining us, you will contribute to cutting-edge graphics technology utilized worldwide. Embrace the opportunity ...

constrained-random verification methodology and reusable componentsExpertise in root-cause analysis of complex issues, with the ability to resolve them efficientlyExcellent knowledge of SystemVerilog and UVMStrong technical leadership skills with experience in mentoring junior engineersAbility to collaborate and drive ideas for wider adoptionYou might also have:GPU/CPU/ ...

constrained-random verification methodology and reusable componentsExpertise in root-cause analysis of complex issues, with the ability to resolve them efficientlyExcellent knowledge of SystemVerilog and UVMStrong technical leadership skills with experience in mentoring junior engineersAbility to collaborate and drive ideas for wider adoptionYou might also have:GPU/CPU/ ...

gate-level simulation, etc.)Knowledge of verifying CPU architectures or other IPFluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, etc. Past verification ownership of a design blockUser knowledge of Linux to enable automation of common tasksKnowledge of versioning tools ...

with design, verification and software driver teams Required Skills and Experience : Experience in hardware verification methodology and planning Programming skills including Hardware Description Languages (SystemVerilog/UVM) Proficiency in problem solving and debugging “Nice To Have” Skills and Experience : Experience with reusing and integrating external VIPs Experience in Python ...

level simulation, etc.) Knowledge of verifying CPU architectures or other IP Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, etc. Past verification ownership of a design block User knowledge of Linux to enable automation of common tasks Knowledge of versioning tools ...

troubleshooting simulation/emulation mismatches and test failures.Hands-on experience with emulation platforms such as ZeBu, Palladium, or Strato.Familiarity with RTL languages such as SystemVerilog/VerilogExperience in collaboration with EDA vendors to introduce new capabilities, resolve tool issues, and contribute to future tool improvements.Skilled in planning system test tasks ...