151 to 175 of 428 Permanent SystemVerilog Jobs

to patents What You Bring 8+ years in secure hardware design Master's/PhD in EE, CE, or similar Strong RTL (Verilog/SystemVerilog), ASIC flow, and scripting (Python/Perl) skills Hands-on with Synopsys/Cadence toolchains Perks Work with top-tier security experts Flexible hybrid setup More ❯

to patents What You Bring 8+ years in secure hardware design Master's/PhD in EE, CE, or similar Strong RTL (Verilog/SystemVerilog), ASIC flow, and scripting (Python/Perl) skills Hands-on with Synopsys/Cadence toolchains Perks Work with top-tier security experts Flexible hybrid setup More ❯

to offer improvements to efficiency and quality for both the design flow and the final product. Required skills: Knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products A strong skillset in delivering digital designs in the ASIC and FPGA industry Optimisation of timing and hardware resources More ❯

Solid understanding of digital design principles, including pipelining, clock domain crossing, and low-power design techniques, high performance design techs. Proficient in Verilog/SystemVerilog/VHDL. Familiar with ASIC design flow and tools. Experience with GPU design or computer graphics architecture. Familiarity with high-speed interfaces and memory subsystems. More ❯

Solid understanding of digital design principles, including pipelining, clock domain crossing, and low-power design techniques, high performance design techs. Proficient in Verilog/SystemVerilog/VHDL. Familiar with ASIC design flow and tools. Experience with GPU design or computer graphics architecture. Familiarity with high-speed interfaces and memory subsystems. More ❯

Solid understanding of digital design principles, including pipelining, clock domain crossing, and low-power design techniques, high performance design techs. Proficient in Verilog/SystemVerilog/VHDL. Familiar with ASIC design flow and tools. Experience with GPU design or computer graphics architecture. Familiarity with high-speed interfaces and memory subsystems. More ❯

to offer improvements to efficiency and quality for both the design flow and the final product. Required skills: Knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products A strong skillset in delivering digital designs in the ASIC and FPGA industry Optimisation of timing and hardware resources More ❯

ll work on designs featuring high-speed serial I/O, PCIe interfaces, and large-scale FPGA deployments. The tooling is standard, (Verilog/SystemVerilog, Verilator, and C++,) what you build needs to be anything but. If the manufacturer thinks it's possible with their hardware, you've not gone More ❯

/hr DOE Clearance Level: Secret Job Requirements • FPGA experience • Experience in UVM, entire process of UVM test benches including architecture, design, and implementation • Systemverilog experience a plus • Nice to have skills: DO-254, PCB design About Performance and Talent Tier: Performance Software and its sister company, Talent Tier, are More ❯

/hr DOE Clearance Level: Secret Job Requirements • FPGA experience • Experience in UVM, entire process of UVM test benches including architecture, design, and implementation • Systemverilog experience a plus • Nice to have skills: DO-254, PCB design About Performance and Talent Tier: Performance Software and its sister company, Talent Tier, are More ❯

ll work on designs featuring high-speed serial I/O, PCIe interfaces, and large-scale FPGA deployments. The tooling is standard, (Verilog/SystemVerilog, Verilator, and C++,) what you build needs to be anything but. If the manufacturer thinks it's possible with their hardware, you've not gone More ❯

ll work on designs featuring high-speed serial I/O, PCIe interfaces, and large-scale FPGA deployments. The tooling is standard, (Verilog/SystemVerilog, Verilator, and C++,) what you build needs to be anything but. If the manufacturer thinks it's possible with their hardware, you've not gone More ❯

player Ability to work across teams and finding solutions to problems Ability to solve design issues through programming, e.g. Python, Tcl Strong competency in SystemVerilog or VHDL Knowledge of digital design flows Capable of managing time and priorities Application specific blocks High-speed serial interfaces Complex third-party IP integration More ❯

level simulation etc ) Knowledge of verifying CPU architectures or other IP Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Analytical thinking and team collaboration skills What we'd love you to have Past verification ownership of a design block More ❯

player Ability to work across teams and finding solutions to problems Ability to solve design issues through programming, e.g. Python, Tcl Strong competency in SystemVerilog or VHDL Knowledge of digital design flows Capable of managing time and priorities Desirable: Processor design Application specific blocks High-speed serial interfaces Complex third More ❯

Parameter Extraction (LPE) Simulations Good written and verbal communication Preferred Qualifications & Experience: Proficient with Cadence Suite (Virtuoso ADE Spectre) HDL programming languages (Verilog/SystemVerilog) Analog Behavioral Models (Verilog-A, Verilog-AMS) Mixed-Signal Verification Why You Will Like Working At ADI: We place great value on individual judgment We More ❯

High-speed I/Os such as DDR or SerDes PHY Proficiency with Cadence Virtuoso Analog circuit modeling with VerilogA, VerilogAMS, and/or SystemVerilog Experience with MOS advanced nodes below 32nm Experience with radiation-hardened electronics Applicants selected for this position will be required to obtain and maintain a More ❯

Parameter Extraction (LPE) Simulations Good written and verbal communication Preferred Qualifications & Experience: Proficient with Cadence Suite (Virtuoso ADE Spectre) HDL programming languages (Verilog/SystemVerilog) Analog Behavioral Models (Verilog-A, Verilog-AMS) Mixed-Signal Verification Why You Will Like Working At ADI: We place great value on individual judgment We More ❯

field. Master's degree preferred. Experience: Extensive experience in design verification, including team and/or project leadership roles. Skills: Proficiency in verification languages (SystemVerilog, UVM), strong analytical and problem-solving skills, excellent communication and leadership abilities. Knowledge of mixed-signal ASIC architectures, real number modelling, constrained random, assertions, gate More ❯

A client of Innova Solutions is immediately hiring a FPGA/ASIC Design Engineer. Position Type: Full time Contract Duration: 04 Months Location: Camden, NJ (Onsite) As a FPGA/ASIC Design Engineer, you will: • The FPGA/ASIC Design More ❯

verification reports demonstrating all tests passing on RTL. Utilize verification methodologies including design checks, simulation, emulation, UVM, formal verification, and testbenches in Verilog/SystemVerilog and C. #J-18808-Ljbffr More ❯

low area, and understanding of how RTL will map to gate-level structures Familiarity with the frontend design flow Experience with hardware description languages - SystemVerilog would be desirable You must be able to relocate to Bristol or already be based in the City. Base and Bonus are on offer. Hybrid More ❯

CSI/DSI Experience of interconnect standards ACE, AXI, AHB, and APB Ability to form requirements and specify architectural features. Expert-level Verilog/SystemVerilog for design and verification. Familiarity with scripting languages. The following would also be useful: The role is based on site in Cambridge with an expectation More ❯

CSI/DSI Experience of interconnect standards ACE, AXI, AHB, and APB Ability to form requirements and specify architectural features. Expert-level Verilog/SystemVerilog for design and verification. Familiarity with scripting languages. The following would also be useful: The role is based on site in Cambridge with an expectation More ❯

partners. Key Responsibilities: Define digital architectures for AI accelerators, data paths, control logic, and SoC subsystems. Develop high-quality, synthesizable RTL in Verilog/SystemVerilog with performance, power, and area optimization in mind. Collaborate cross-functionally with verification, physical design, and packaging teams to ensure seamless integration. Leverage Cadence digital More ❯