26 to 50 of 52 Permanent SystemVerilog Jobs

deliver high-performance solutions Stay at the forefront of FPGA technology and help shape our roadmap What we're looking for Strong FPGA design background (VHDL/Verilog/SystemVerilog) Experience leading or mentoring engineering teams Proven delivery of complex FPGA systems Solid grasp of RTL design, timing closure, verification, and integration Confident communicator who thrives on problem-solving and More ❯

not just depth: the digital cores are the nexus of these mixed-signal chips, tying everything together. ?? What youll be doing End-to-end RTL design using Verilog/SystemVerilog Designing synchronous and asynchronous state machines and control logic Working on analog/digital partitioning and functional modelling FPGA emulation, lab validation, post-design analysis, and place & route support Collaborating More ❯

Duration: 5/6 Months Hybrid Job Description: We are seeking a highly skilled and meticulous SystemVerilog/UVM Design Verification Test Engineer to play a crucial role in validating our complex System-on-Chip (SOC) and Integrated Circuit (IC) designs. This role requires expert-level proficiency in SystemVerilog and UVM, a strong understanding of processor architectures, and high-speed … protocols. Responsibilities: Architect, develop, and maintain advanced verification environments (Testbenches) using UVM and SystemVerilog to ensure functional correctness and achieve aggressive coverage goals for complex SOC features. Develop and execute comprehensive verification test plans for key SOC blocks, with a focus on ARM processor subsystems and high-speed interfaces. Implement test cases and scenarios to rigorously verify the functionality and … bugs, and contribute to post-silicon validation strategy. Experience (Required): 3+ years of professional experience specifically in IC/SOC Design Verification (DV). Mandatory expert-level proficiency in SystemVerilog and UVM (Universal Verification Methodology). Demonstrated ability to build UVM testbenches from scratch and contribute significantly to UVM environment architecture. Demonstrated experience verifying processor subsystems (e.g., CPU clusters, interconnects More ❯

Overview Bowhead is seeking a FPGA Engineer to join our team that supports the Hypersonics Projectiles Division of the Naval Surface Warfare Center Dahlgren and contribute to the development of high-performance digital systems. In this role, you will design More ❯

integration with high-speed ADCs/DACs. Support test and lab evaluation using signal generators, spectrum analysers, and oscilloscopes. Lead or contribute to the implementation of designs using VHDL, SystemVerilog, and MATLAB/Simulink HDL Coder. Develop C/C++ software for deployment to embedded systems Use industry-standard tools such as Vivado, Quartus, and ModelSim for simulation, synthesis, and …/firmware design testing (Oscilloscopes, signal generators and logic analysers) Desirable Experience Experience working with embedded Linux, bare-metal C drivers, or FPGA-based system integration Proficiency in VHDL, SystemVerilog, and embedded C for FPGA-host integration, control, and testing Familiarity with AXI interfaces, memory interfaces, JESD204B/C, or high-speed ADC/DAC integration Experience designing streaming architectures More ❯

Working for a cutting edge semiconductor company, I have a high-profile role available, as Chief Architect/Chief NPU Architect. You will be part of key R&D projects for complex CPU/NPU/GPU related architecture requirements More ❯

Working for a cutting edge semiconductor company, I have a high-profile role available, as Chief Architect/Chief NPU Architect. You will be part of key R&D projects for complex CPU/NPU/GPU related architecture requirements More ❯

Working for a cutting edge semiconductor company, I have a high-profile role available, as Chief Architect/Chief NPU Architect. You will be part of key R&D projects for complex CPU/NPU/GPU related architecture requirements More ❯

FPGA Engineer/Senior FPGA Engineer My client, a trailblazer in advanced security technology, excels in creating high-integrity critical systems where flawless performance is non-negotiable. They continually push boundaries to exceed customer and stakeholder expectations, making excellence their More ❯

Our client is seeking Firmware Engineers for contracts based in Luton, Bedfordshire. The Firmware Engineer will deliver Firmware for complex digital systems that meet challenging future customer requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM More ❯

Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh More ❯

Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh More ❯

Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh More ❯

Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh More ❯

ASIC Verification Engineer Bristol or Cambridge 3 days onsite work Leading compensation and benefits package This is a superb opportunity to join one of the hottest names in the industry! A chance to build a technology that transforms the future More ❯

closure to achieve first-silicon success. Key Responsibilities Collaborate with design and architecture teams to define and implement verification strategies for AI accelerator blocks and SoC subsystems. Build scalable SystemVerilog/UVM testbenches, including test plans, monitors, checkers, scoreboards, and constrained-random stimulus. Perform coverage-driven and assertion-based verification, analyse coverage reports, and close functional and code coverage gaps. … incorporating high-level models and test generators. Qualifications Proven experience in digital IC design verification, preferably with exposure to CPU, GPU, NPU, or AI accelerator IP. Strong skills in SystemVerilog, UVM, and scripting languages such as Python, C++, Perl, or TCL. Solid understanding of computer architecture, memory hierarchies, and standard interconnects (e.g., AMBA/AXI, NoC). Familiarity with formal More ❯

Brand new, and cutting edge project, working for an exciting scale-up in the semiconductor space - to be based full-time from Scotland. Salary is circa £100k (PLUS AMAZING ADDITIONAL PACKAGE) I am looking for a SOC Chip design Lead More ❯

design and architecture teams to create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or multi chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design and DV engineers to implement the test plan … MS in Electrical Engineering, Computer Engineering or Computer Science 8+ years and current hands-on experience in block-level/IP-level/SOC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based testbenches Experience with modern programming languages like Python Knowledge of ARM AMBA protocols such as More ❯

RISC-V cores, OTBN (cryptographic CPU), AES accelerators, and peripherals like USB, I2C, and SPI. Key Responsibilities Design, implement, and debug block/system-level tests and testbenches using SystemVerilog and UVM Develop test and coverage plans for new and updated designs Triage and debug nightly regressions Review contributions to open-source projects Enhance test and CI infrastructure Collaborate on … academic/industry publications Stay current with verification best practices and introduce improvements Candidate Requirements Essential: 5+ years industry experience in design verification Strong SystemVerilog and UVM expertise Experience across the full verification cycle (planning to tape-out) Able to provide estimates and coordinate with project managers Comfortable in multidisciplinary, multi-organisation teams Familiar with Git and code review tools More ❯

in every design you deliver. What you’ll do Work closely with hardware designers and system architects to define and own verification plans based on design specifications Develop scalable SystemVerilog testbenches , including checkers, coverage groups, and reference models Design and run self-checking, directed, and randomized tests Maintain the verification environment, including tracking regressions, bugs, and coverage metrics Drive quality … level designs Core skills Strong commercial experience in functional verification , with ownership of verification strategy and planning Expertise in testbench design using frameworks like UVM or OVM Proficiency with SystemVerilog assertions (SVA) Familiarity with multiple programming languages (e.g., C, C++, Python ) Visa sponsorship will be provided for candidates who require. Please note, you must already be living and working in More ❯

in every design you deliver. What you’ll do Work closely with hardware designers and system architects to define and own verification plans based on design specifications Develop scalable SystemVerilog testbenches , including checkers, coverage groups, and reference models Design and run self-checking, directed, and randomized tests Maintain the verification environment, including tracking regressions, bugs, and coverage metrics Drive quality … level designs Core skills Strong commercial experience in functional verification , with ownership of verification strategy and planning Expertise in testbench design using frameworks like UVM or OVM Proficiency with SystemVerilog assertions (SVA) Familiarity with multiple programming languages (e.g., C, C++, Python ) Visa sponsorship will be provided for candidates who require. Please note, you must already be living and working in More ❯

in every design you deliver. What you’ll do Work closely with hardware designers and system architects to define and own verification plans based on design specifications Develop scalable SystemVerilog testbenches , including checkers, coverage groups, and reference models Design and run self-checking, directed, and randomized tests Maintain the verification environment, including tracking regressions, bugs, and coverage metrics Drive quality … level designs Core skills Strong commercial experience in functional verification , with ownership of verification strategy and planning Expertise in testbench design using frameworks like UVM or OVM Proficiency with SystemVerilog assertions (SVA) Familiarity with multiple programming languages (e.g., C, C++, Python ) Visa sponsorship will be provided for candidates who require. Please note, you must already be living and working in More ❯

data analysis. "Nice To Have" Skills and Experience : Experience with SoC-level performance analysis and tools. Familiarity with memory subsystem micro-architecture and performance implications. Experience with Verilog/SystemVerilog RTL, including analysis and debugging in collaboration with design teams. Working knowledge of AMBA protocols and transaction-level modeling (SystemC/TLM). Exposure to Verilog/SystemVerilog and interaction More ❯

Job Description:, ALL CAPS, NO SPACES B/T UNDERSCORES PTN_US_GBAMSREQID_CandidateBeelineID, i.e. PTN_US SKIPJOHNSON0413 Bill Rate: $80.0085.00 GBaMS ReqID: , MSP Owner: Jenell, Location: Cupertino, CA (5x/week onsite), Duration: 6 months Demonstrable track record of More ❯

Development Verification Engineer £55,000 - £65,000 + Training + Progression + 10% Bonus Bristol - Hybrid Are you a Development Verification Engineer or similar with expertise in SystemVerilog and UVM, seeking an autonomous role where your work directly contributes to the success of a leading semiconductor company, with opportunities for career growth, ongoing development, and the potential to increase your … turnover in the billions and a strong global presence, they support clients in driving efficiency, safety, and sustainability across critical industries. In this role, you will develop and maintain SystemVerilog, UVM test benches, create new verification components, debug test cases, define functional coverage models, while supporting test bench architecture and design reviews using industry standard EDA tools. This is a … full-time role, Monday to Friday, 09:00AM - 17:00PM, with two days per week working from home. This role would suit a Development Verification Engineer with SystemVerilog and UVM skills, looking to join a world-leading semiconductor company with clear progression, specialist training, and the opportunity to boost earnings through a company bonus. The Role: Take the lead in More ❯