326 to 350 of 465 Permanent SystemVerilog Jobs

gate level simulation etc ) Knowledge of verifying CPU architectures or other complex IP (e.g. GPUs, NNAs) Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Past verification ownership of multiple design blocks Analytical thinking, self-sufficiency and strong team collaboration skills Ability to work effectively across teams to debug issues More ❯

Computer Engineering, or a related field. Master's degree preferred. Experience: Extensive experience in design verification, including team and/or project leadership roles. Skills: Proficiency in verification languages (SystemVerilog, UVM), strong analytical and problem-solving skills, excellent communication and leadership abilities. Knowledge of mixed-signal ASIC architectures, real number modelling, constrained random, assertions, gate-level simulations, functional/code More ❯

Are you a passionate engineer who wants to join a verification team using leading-edge tools and methodologies? Do you want to be part of the growth of our Design Center in Bristol? Are you fascinated by the future of More ❯

Are you a passionate engineer who wants to join a verification team using leading-edge tools and methodologies? Do you want to be part of the growth of our Design Center in Bristol? Are you fascinated by the future of More ❯

Senior FPGA Engineer £80-100k Slough Hybrid My client's innovative technologies have facilitated the deployment of high-speed internet and robust communication networks for remote and underserved areas, fostering digital inclusion and supporting the growth of smart cities More ❯

Social network you want to login/join with: col-narrow-left Client: microTECH Global Ltd Location: Edinburgh, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Reference: 83bfbdd7c7bf Job Views: 15 Posted: 17.06.2025 Expiry More ❯

ASIC Design Engineer Edinburgh Global Semiconductor leader As an ASIC Design engineer, you will get the opportunity to work in the beautiful City of Edinburgh. Working in the heart of Edinburgh means being surrounded by stunning architecture, rich history, and More ❯

Senior Verification Engineer - Ghent I am seeking a highly experienced Senior Verification Engineer to join a leading organisation at the forefront of semiconductor innovation. This is an exceptional opportunity to be part of a dynamic and multicultural team, working on More ❯

Social network you want to login/join with: col-narrow-left Client: Enterprise Recruitment Ltd Location: portsmouth, hampshire, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 4 Posted: 16.06.2025 Expiry Date: 31.07.2025 More ❯

Swedium Global Services is a growing System Engineering and Solution Company, offering services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy, and Outsourcing services to our clients More ❯

Senior FPGA Engineer £80-100k Slough Hybrid My client's innovative technologies have facilitated the deployment of high-speed internet and robust communication networks for remote and underserved areas, fostering digital inclusion and supporting the growth of smart cities More ❯

Senior FPGA Engineer | £80-100k | Slough | Hybrid My client's innovative technologies have facilitated the deployment of high-speed internet and robust communication networks for remote and underserved areas, fostering digital inclusion and supporting the growth of smart cities More ❯

They're looking for a Staff Verification Engineer. Principal Verification Engineer Responsibilities: Develop and execute verification plans in collaboration with design and systems teams. Create and maintain testbenches using SystemVerilog, UVM. Work closely with RTL designers to understand architectural intent and corner cases. Write and review functional coverage models to ensure complete design verification. Requirements: Extensive experience with SystemVerilog and More ❯

They're looking for a Staff Verification Engineer. Principal Verification Engineer Responsibilities: Develop and execute verification plans in collaboration with design and systems teams. Create and maintain testbenches using SystemVerilog, UVM. Work closely with RTL designers to understand architectural intent and corner cases. Write and review functional coverage models to ensure complete design verification. Requirements: Extensive experience with SystemVerilog and More ❯

They're looking for a Staff Verification Engineer. Principal Verification Engineer Responsibilities: Develop and execute verification plans in collaboration with design and systems teams. Create and maintain testbenches using SystemVerilog, UVM. Work closely with RTL designers to understand architectural intent and corner cases. Write and review functional coverage models to ensure complete design verification. Requirements: Extensive experience with SystemVerilog and More ❯

They're looking for a Staff Verification Engineer. Principal Verification Engineer Responsibilities: Develop and execute verification plans in collaboration with design and systems teams. Create and maintain testbenches using SystemVerilog, UVM. Work closely with RTL designers to understand architectural intent and corner cases. Write and review functional coverage models to ensure complete design verification. Requirements: Extensive experience with SystemVerilog and More ❯

analysis. Provide verification reports to demonstrate all tests passing on the RTL. Utilize methodologies including design checks, verification techniques with simulators and emulators such as UVM, formal, Verilog/SystemVerilog testbenches, and C, SystemVerilog, UVM test cases. #J-18808-Ljbffr More ❯

be, please get in touch. 1. Verification Lead (Permanent) Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Leadership role managing SoC/IP-level verification Requirements: 6+ years’ experience, strong SystemVerilog/UVM, team mentorship 2. Hardware Verification Engineer (Permanent/Contract) Location: Hemel Hempstead, UK (Hybrid Preferred | Remote Considered) Type: Contract (Outside IR35) Focus: RISC-V, GPU, AI, complex SoCs … Requirements: 5+ years’ experience, SystemVerilog/UVM, scripting 3. Junior/Mid-Level Verification Engineer (Permanent) Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Perfect for engineers early in their verification careers Requirements: 1+ year experience, familiarity with SystemVerilog/UVM If any of these sound like a fit, please feel free to reach out or send your CV. If these More ❯

be, please get in touch. 1. Verification Lead (Permanent) Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Leadership role managing SoC/IP-level verification Requirements: 6+ years’ experience, strong SystemVerilog/UVM, team mentorship 2. Hardware Verification Engineer (Permanent/Contract) Location: Hemel Hempstead, UK (Hybrid Preferred | Remote Considered) Type: Contract (Outside IR35) Focus: RISC-V, GPU, AI, complex SoCs … Requirements: 5+ years’ experience, SystemVerilog/UVM, scripting 3. Junior/Mid-Level Verification Engineer (Permanent) Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Perfect for engineers early in their verification careers Requirements: 1+ year experience, familiarity with SystemVerilog/UVM If any of these sound like a fit, please feel free to reach out or send your CV. If these More ❯

be, please get in touch. 1. Verification Lead (Permanent) Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Leadership role managing SoC/IP-level verification Requirements: 6+ years experience, strong SystemVerilog/UVM, team mentorship 2. Hardware Verification Engineer (Permanent/Contract) Location: Hemel Hempstead, UK (Hybrid Preferred | Remote Considered) Type: Contract (Outside IR35) Focus: RISC-V, GPU, AI, complex SoCs … Requirements: 5+ years experience, SystemVerilog/UVM, scripting 3. Junior/Mid-Level Verification Engineer (Permanent) Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Perfect for engineers early in their verification careers Requirements: 1+ year experience, familiarity with SystemVerilog/UVM If any of these sound like a fit, please feel free to reach out or send your CV. If these More ❯

on analysis of coverage gaps. Provide verification reports showing all tests passing on the RTL. Methodologies include design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM test cases. #J-18808-Ljbffr More ❯

on coverage gap analysis. Provide verification reports showing all tests passing on the RTL. Use methodologies including design checks, verification techniques with simulators and emulators: UVM, formal, Verilog/SystemVerilog testbenches, C, SystemVerilog, UVM test cases. #J-18808-Ljbffr More ❯

analysis of coverage gaps. Provide verification reports showing all tests passing on the RTL. Use methodologies including design checks, verification techniques with simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM based test cases. #J-18808-Ljbffr More ❯

of coverage gaps. Provide verification reports showing all implemented tests passing on the RTL. Utilize methodologies including design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM based test cases. #J-18808-Ljbffr More ❯

based on analysis of coverage gaps. Provide verification reports demonstrating all tests passing on RTL. Utilize methodologies including design checks, verification with simulators and emulators: UVM, formal, Verilog/SystemVerilog testbenches, and C, SystemVerilog, UVM test cases. #J-18808-Ljbffr More ❯