351 to 375 of 611 Permanent SystemVerilog Jobs

bachelor's degree. Additional Job Requirements: Applicants should possess solid skills in front-end digital systems design with experience in design flows from Cadence or Synopsys. Be fluent in SystemVerilog, Verilog, or VHDL, and familiar with LINT, simulation, and synthesis. Familiarity with architectures for secure systems design (e.g., cryptographic encoders/decoders or tagged processor architectures) is a plus. Demonstrated More ❯

imaging systems. The position is based in our Design Centre in Edinburgh, Scotland. JOB RESPONSIBILITIES: Define concepts for digital SoC architecture and blocks Create specifications Design and verify RTL (SystemVerilog/VHDL/FPGA) Collaborate closely with analog IC designers and subcontractors Experience with synthesis, timing closure, and STA is highly desirable Support DfT strategy and implementation Debug RTL and More ❯

Pro Standards, Frameworks and Techniques: Knowledge and experience of safety standards such as IEC 61513, IEC 62566, IEC 26262, DO-254 UVM Constrained Random Testing Formal Verification Languages: VHDL, SystemVerilog, TCL, Python The package: You'll receive a very competitive salary ( offered depends on level of experience) and other benefits including pension, life assurance and 25 days' (plus bank holidays More ❯

and do not include bonus, equity, or benefits. Learn more about benefits at Google ( ) . + Define microarchitecture details, block diagrams, data flow, pipelines, etc. + Perform RTL development (SystemVerilog), debug functional/performance simulations. + Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks. + Participate in synthesis, timing/power estimation and FPGA/silicon bring-up. More ❯

and planning skills Motivated, self-starting, and collaborative Ability to troubleshoot complex issues across teams and languages Experience with verification in CPU and/or ASIC environments Knowledge of SystemVerilog, Python, C++, Linux, UVM, SVA, Assembly, LLVM, GCC, Git, SGE or other DRS Familiarity with XML, XPath/XSLT We offer a competitive salary, flexible working, generous leave, private medical More ❯

mass production Strong background in post-silicon test optimization and yield analysis Experience defining and implementing test strategies for high-volume production Proficiency in RTL and testbench development using SystemVerilog and Verilog Strong scripting skills (Shell, Tcl, Python3) Experience with Tessent and SSN methods integrated with EDA design flows is a plus Excellent leadership and communication skills Reporting structure: Reports More ❯

run software that tests digital designs in simulation and bringup You have: BS degree in Computer Engineering or equivalent practical experience 5+ years of industry experience with Verilog and SystemVerilog, RTL digital microarchitecture Knowledge of computer architecture and on-chip communication networks (e.g. AXI) Experience with industry standard protocols, interfaces, and IP components, such as PCIe, DDR, MIPI, Ethernet, and More ❯

SOC-level verification Ability to determine verification requirements from the analysis of specifications Experience of debug and testing methodologies Experience with industry-standard verification methodologies and tools (UVM/SystemVerilog, Tools like VCS/Cadence/Questa) Experience in version control systems (e.g., Git/Mercurial/Perforce/Subversion) You might also have: A background in digital design Confident More ❯

Engineering or related. Additional Job Description: Applicants should possess solid skills in front-end digital systems design with experience in design flows from Cadence or Synopsys. Be fluent in SystemVerilog, Verilog or VHDL and familiar with LINT, simulation and synthesis. Familiarity with architectures for secure systems design, e.g., cryptographic encoders/decoders or tagged processor architectures is a plus. Applicants More ❯

Engineering or related. Additional Job Description: Applicants should possess solid skills in front-end digital systems design with experience in design flows from Cadence or Synopsys. Be fluent in SystemVerilog, Verilog or VHDL and familiar with LINT, simulation and synthesis. Familiarity with architectures for secure systems design, e.g., cryptographic encoders/decoders or tagged processor architectures is a plus. Demonstrated More ❯

Engineering or related. Additional Job Description: Applicants should possess solid skills in front-end digital systems design with experience in design flows from Cadence or Synopsys. Be fluent in SystemVerilog, Verilog or VHDL and familiar with LINT, simulation and synthesis. Familiarity with architectures for secure systems design, e.g., cryptographic encoders/decoders or tagged processor architectures is a plus. Demonstrated More ❯

Propagation, Linting Experience with Perl, Python or other scripting language 'Nice to Have' Skills and Experience: Experience with ARM-based designs and/or ARM System Architectures Experience with SystemVerilog and verification methodologies - UVM/OVM/e Experience leading small teams or projects Experience or knowledge in the following areas Synthesis and timing analysis Power management techniques DFT and More ❯

Propagation, Linting Experience with Perl, Python or other scripting language 'Nice to Have' Skills and Experience: Experience with ARM-based designs and/or ARM System Architectures Experience with SystemVerilog and verification methodologies - UVM/OVM/e Experience leading small teams or projects Experience or knowledge in the following areas Synthesis and timing analysis Power management techniques DFT and More ❯

Power Distribution, Spice Circuit analysis Experience with Place and Route, digital implementation Experience with EDA tools from Synopsys (ICC2, DC, PT), Cadence (Genus, Innovus, Voltus) Experience with Verilog/SystemVerilog Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for More ❯

Power Distribution, Spice Circuit analysis Experience with Place and Route, digital implementation Experience with EDA tools from Synopsys (ICC2, DC, PT), Cadence (Genus, Innovus, Voltus) Experience with Verilog/SystemVerilog Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for More ❯

design techniques to keep Flux at the forefront of silicon quality. Skills & Experience 7+years in digital ASIC/SoC design & verification, with at least two tape‐outs. Mastery of SystemVerilog/UVM, functional coverage, constraint‐random stimulus and scoreboards. Deep understanding of clock‐domain crossing, reset and power‐domain management, DFT/scan and low‐power (UPF/CPF) methodologies. More ❯

using Mentor Graphics Xpedition tools High speed digital signal integrity simulation using Hyperlynx, HFSS, or ADS Experience developing embedded software and software using C, C++ Experience RTL development using SystemVerilog Familiarity with AMD FPGAs and design tools Project leadership Salary Range: $100,300.00 - $150,500.00Salary Range 2: $124,900.00 - $187,300.00 The above salary range represents a general guideline; however More ❯

using Mentor Graphics Xpedition tools High speed digital signal integrity simulation using Hyperlynx, HFSS, or ADS Experience developing embedded software and software using C, C++ Experience RTL development using SystemVerilog Familiarity with AMD FPGAs and design tools Project leadership Salary Range: $100,300.00 - $150,500.00Salary Range 2: $124,900.00 - $187,300.00 The above salary range represents a general guideline; however More ❯

using Mentor Graphics Xpedition tools High speed digital signal integrity simulation using Hyperlynx, HFSS, or ADS Experience developing embedded software and software using C, C++ Experience RTL development using SystemVerilog Familiarity with AMD FPGAs and design tools Project leadership Salary Range: $100,300.00 - $150,500.00Salary Range 2: $124,900.00 - $187,300.00 The above salary range represents a general guideline; however More ❯

PhD degree with 6+ years or MS with 10+ years of industry experience in digital and mixed-signal design Experience working with machine-learning architectures Experienced with Verilog or SystemVerilog RTL design Experience running front-to-back suite of digital integration tools such as VCS, Verdi, Design Compiler, Fusion Compiler, Innovus, Primetime, StarRC, Formality or equivalent tools. Good top-down More ❯

for defining, estimating and tracking of own work YOU SHOULD HAVE: Over 2 years recent and relevant module design experience within at least one HDL (VHDL/Verilog/SystemVerilog) Knowledge of computer systems and architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning tools (Git, SVN) Knowledge of More ❯

for defining, estimating and tracking of own work YOU SHOULD HAVE: Over 2 years recent and relevant module design experience within at least one HDL (VHDL/Verilog/SystemVerilog) Knowledge of computer systems and architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning tools (Git, SVN) Knowledge of More ❯

Join to apply for the Senior Firmware Engineer role at Fortescue 3 days ago Be among the first 25 applicants Join to apply for the Senior Firmware Engineer role at Fortescue Get AI-powered advice on this job and more More ❯

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This opportunity is for an engagement focused Product Engineer (PE) in the Digital and Signoff Group (DSG) at Cadence. The More ❯

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to More ❯