inclusivity, innovation, and forward-thinking leadership What You ll Bring 5+ years in firmware/FPGA design, with experience in architecture or technical leadership Deep knowledge of VHDL/SystemVerilog, high-speed digital design, and simulation Comfortable capturing and refining requirements from stakeholders Experience in defence, aerospace, or safety-critical embedded systems preferred Eligibility for UK Security Clearance is essential More ❯
Belfast, County Antrim, Northern Ireland, United Kingdom
Morson Talent
inclusivity, innovation, and forward-thinking leadership What You'll Bring 5+ years in firmware/FPGA design, with experience in architecture or technical leadership Deep knowledge of VHDL/SystemVerilog, high-speed digital design, and simulation Comfortable capturing and refining requirements from stakeholders Experience in defence, aerospace, or safety-critical embedded systems preferred Eligibility for UK Security Clearance is essential More ❯
inclusivity, innovation, and forward-thinking leadership What You'll Bring 5+ years in firmware/FPGA design, with experience in architecture or technical leadership Deep knowledge of VHDL/SystemVerilog, high-speed digital design, and simulation Comfortable capturing and refining requirements from stakeholders Experience in defence, aerospace, or safety-critical embedded systems preferred Eligibility for UK Security Clearance is essential More ❯
test generation, coverage collection, gate level simulation etc ) Knowledge of verifying CPU architectures or other IP Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Analytical thinking and team collaboration skills What we'd love you to have Past verification ownership of a design block User knowledge of Linux to More ❯
Role - DV Engineer Location: EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage More ❯
We are looking for an RTL Design Engineer with a strong background in digital design and SoC development to join our dynamic hardware team. The ideal candidate will bring deep expertise in AXI protocol integration, CDC/RDC analysis, and More ❯
Social network you want to login/join with: Design Verification Engineer, leeds, west yorkshire col-narrow-left Client: ALOIS Solutions Location: leeds, west yorkshire, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views More ❯
Social network you want to login/join with: Application Specific Integrated Circuit Design Engineer, bath col-narrow-left Client: IC Resources Location: bath, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 2 More ❯
• Verify CPU connectivity to IP blocks (using ASM boot , and C code, GNU toolchain ) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design More ❯
Social network you want to login/join with: Design Verification Engineer, Watford, Hertfordshire Client: ALOIS Solutions Location: Watford, Hertfordshire, United Kingdom Job Category: Other EU work permit required: Yes Job Views: 1 Posted: 31.05.2025 Expiry Date: 15.07.2025 Job Description More ❯
Social network you want to login/join with: Design Verification Engineer, sheffield, south yorkshire col-narrow-left Client: ALOIS Solutions Location: sheffield, south yorkshire, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views More ❯
Social network you want to login/join with: Design Verification Engineer, south west london Client: ALOIS Solutions Location: south west london, United Kingdom Job Category: Other - EU work permit required: Yes Job Views: 1 Posted: 31.05.2025 Expiry Date: 15.07.2025 More ❯
Social network you want to login/join with: Design Verification Engineer, peterborough col-narrow-left Client: ALOIS Solutions Location: peterborough, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 8 Posted: 10.06.2025 Expiry More ❯
• Verify CPU connectivity to IP blocks (using ASM boot , and C code, GNU toolchain ) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design More ❯
Social network you want to login/join with: Design Verification Engineer, northampton col-narrow-left Client: ALOIS Solutions Location: northampton, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 1 Posted: 31.05.2025 Expiry More ❯
Social network you want to login/join with: col-narrow-left Client: Apple Location: Cambridge, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Reference: aff36e91952e Job Views: 2 Posted: 02.06.2025 Expiry Date: 17.07.2025 More ❯
Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing More ❯
Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing More ❯
Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing More ❯
Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing More ❯
Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing More ❯
Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing More ❯
Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing More ❯
Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing More ❯
Job Description: The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI, Ethernet and AXI to drive the internal components and send data. Responsibilities: UVM More ❯
