26 to 50 of 94 Permanent Verilog Jobs

the role of Firmware/Embedded Software Engineer include: Designing and developing embedded software and firmware from concept to release Programming ARM-based microcontrollers and FPGA systems (VHDL/Verilog) Implementing real-time systems and signal processing algorithms Collaborating with hardware engineers to integrate and optimise product performance Contributing to design documentation, testing, and validation processes Skills and experience required More ❯

on robust, real-time, and embedded FPGA development. The Role: As an FPGA Engineer, you will take an active role in the design, verification, and delivery of VHDL/Verilog-based solutions for complex integrated systems. Collaborating closely with systems, hardware, and software teams, you’ll tackle integration challenges and drive innovation in high-performance environments. Key Responsibilities: Develop and More ❯

in a professional R&D environment, ideally including formal processes and product delivery. A master's degree in engineering, electronics, computer science, or a related field. Experience with VHDL (Verilog or SV experience also acceptable), Python, and ideally also Rust. Insightful hands-on experience with industry-standard EDA flows and methodologies. Experience with verification frameworks like UVM, cocotb or similar More ❯

power electronics. This is a senior embedded systems engineer role mainly focussed on FPGA design using mainly VHDL or Verilog. Key skills: FPGA design using VHDL and/or Verilog Software development in C/C++ for embedded processors Circuit design, implementation, and bench level testing Strong teamwork and communication skills Experience of schematic capture and PCB layout in Altium More ❯

signal processing theory Commercial experienceof Radio Systems design withexposure to GNSS, Smart Antennas, Beamforming and Jammers all highly beneficial Proficiency in MATLAB, Python, C/C++, or VHDL/Verilog for simulation and implementation Understanding of real-time systems and embedded platforms Whats on Offer to the successful Senior DSP & CommunicationsEngineer: Salary up to C£85,000 depending on experience More ❯

senior group will deliver high-speed compute infrastructure integrated directly into trading, research, and networking pipelines. What You’ll Be Doing Designing and implementing latency-optimised FPGA systems in Verilog/SystemVerilog Developing high-speed modules (PCIe, Ethernet, DDR/QDR) with deep pipelining Using simulation and formal tools (Verilator, Cocotb, etc.) for validation Working across teams (ASIC, software, infra More ❯

senior group will deliver high-speed compute infrastructure integrated directly into trading, research, and networking pipelines. What You’ll Be Doing Designing and implementing latency-optimised FPGA systems in Verilog/SystemVerilog Developing high-speed modules (PCIe, Ethernet, DDR/QDR) with deep pipelining Using simulation and formal tools (Verilator, Cocotb, etc.) for validation Working across teams (ASIC, software, infra More ❯

senior group will deliver high-speed compute infrastructure integrated directly into trading, research, and networking pipelines. What You'll Be Doing Designing and implementing latency-optimised FPGA systems in Verilog/SystemVerilog Developing high-speed modules (PCIe, Ethernet, DDR/QDR) with deep pipelining Using simulation and formal tools (Verilator, Cocotb, etc.) for validation Working across teams (ASIC, software, infra More ❯

senior group will deliver high-speed compute infrastructure integrated directly into trading, research, and networking pipelines. What You’ll Be Doing Designing and implementing latency-optimised FPGA systems in Verilog/SystemVerilog Developing high-speed modules (PCIe, Ethernet, DDR/QDR) with deep pipelining Using simulation and formal tools (Verilator, Cocotb, etc.) for validation Working across teams (ASIC, software, infra More ❯

senior group will deliver high-speed compute infrastructure integrated directly into trading, research, and networking pipelines. What You’ll Be Doing Designing and implementing latency-optimised FPGA systems in Verilog/SystemVerilog Developing high-speed modules (PCIe, Ethernet, DDR/QDR) with deep pipelining Using simulation and formal tools (Verilator, Cocotb, etc.) for validation Working across teams (ASIC, software, infra More ❯

senior group will deliver high-speed compute infrastructure integrated directly into trading, research, and networking pipelines. What You’ll Be Doing Designing and implementing latency-optimised FPGA systems in Verilog/SystemVerilog Developing high-speed modules (PCIe, Ethernet, DDR/QDR) with deep pipelining Using simulation and formal tools (Verilator, Cocotb, etc.) for validation Working across teams (ASIC, software, infra More ❯

C Bonus/"nice-to-have" skills: Industry experience in RTL design/RTL coding/digital design/hardware design - for FPGA/ASIC (VHDL and/or Verilog, System verilog) Digital Verification (UVM/system verilog) OR Formal verification methods - Jasper Gold, C/system C Definition of complex architecture High-speed digital connectivity and protocols - Fabric, Serdes More ❯

C Bonus/"nice-to-have" skills: Industry experience in RTL design/RTL coding/digital design/hardware design - for FPGA/ASIC (VHDL and/or Verilog, System verilog) Digital Verification (UVM/system verilog) OR Formal verification methods - Jasper Gold, C/system C Definition of complex architecture High-speed digital connectivity and protocols - Fabric, Serdes More ❯

C Bonus/"nice-to-have" skills: Industry experience in RTL design/RTL coding/digital design/hardware design - for FPGA/ASIC (VHDL and/or Verilog, System verilog) Digital Verification (UVM/system verilog) OR Formal verification methods - Jasper Gold, C/system C Definition of complex architecture High-speed digital connectivity and protocols - Fabric, Serdes More ❯

on exciting and groundbreaking projects in a multitude of industries. Skills and Experience Required: Degree in relevant electronics field Knowledge and experience with FPGA development with either VHDL or Verilog Experience with FPGA synthesis Understanding of SOC Architectures The competitive salary is between £45,000 - £65,000 with additional benefits such as remote working from home, and a lot of More ❯

developing test strategies Integrating and verifying designs Ensuring all firmware development aligns with industry and internal standards ✅ What We’re Looking For Proven experience in FPGA design (VHDL/Verilog) Strong background in digital electronics and embedded systems Familiarity with defence or safety-critical environments (preferred) SC clearance or the ability to obtain it 💼 Why Join? Outside IR35 – full control More ❯

developing test strategies Integrating and verifying designs Ensuring all firmware development aligns with industry and internal standards ✅ What We’re Looking For Proven experience in FPGA design (VHDL/Verilog) Strong background in digital electronics and embedded systems Familiarity with defence or safety-critical environments (preferred) SC clearance or the ability to obtain it 💼 Why Join? Outside IR35 – full control More ❯

developing test strategies Integrating and verifying designs Ensuring all firmware development aligns with industry and internal standards ✅ What We’re Looking For Proven experience in FPGA design (VHDL/Verilog) Strong background in digital electronics and embedded systems Familiarity with defence or safety-critical environments (preferred) SC clearance or the ability to obtain it 💼 Why Join? Outside IR35 – full control More ❯

developing test strategies Integrating and verifying designs Ensuring all firmware development aligns with industry and internal standards ✅ What We’re Looking For Proven experience in FPGA design (VHDL/Verilog) Strong background in digital electronics and embedded systems Familiarity with defence or safety-critical environments (preferred) SC clearance or the ability to obtain it 💼 Why Join? Outside IR35 – full control More ❯

Ethernet, SPI) Proven ability to take technical ownership, collaborate effectively, and deliver complex projects Position: Senior FPGA Engineer Location: Cambridge Salary: £70k£160k + equity Key Skills: FPGA, DSP, Verilog/VHDL, high-speed interfaces Desirable: RF experience More ❯

discipline. • Experience of designing FPGA IP cores or sub-systems. • Designing FPGA architectures from a technical specification. • Design with AMD/Intel FPGA and CPLD devices. • Using VHDL/Verilog HDL languages for FPGA design. • Implementing high speed, multi-frequency clocking architectures. • Designing (code entry to timing analysis) using Intel and/or Xilinx FPGA tool sets. • Designing for high More ❯

discipline. • Experience of designing FPGA IP cores or sub-systems. • Designing FPGA architectures from a technical specification. • Design with AMD/Intel FPGA and CPLD devices. • Using VHDL/Verilog HDL languages for FPGA design. • Implementing high speed, multi-frequency clocking architectures. • Designing (code entry to timing analysis) using Intel and/or Xilinx FPGA tool sets. • Designing for high More ❯

discipline. • Experience of designing FPGA IP cores or sub-systems. • Designing FPGA architectures from a technical specification. • Design with AMD/Intel FPGA and CPLD devices. • Using VHDL/Verilog HDL languages for FPGA design. • Implementing high speed, multi-frequency clocking architectures. • Designing (code entry to timing analysis) using Intel and/or Xilinx FPGA tool sets. • Designing for high More ❯

discipline. • Experience of designing FPGA IP cores or sub-systems. • Designing FPGA architectures from a technical specification. • Design with AMD/Intel FPGA and CPLD devices. • Using VHDL/Verilog HDL languages for FPGA design. • Implementing high speed, multi-frequency clocking architectures. • Designing (code entry to timing analysis) using Intel and/or Xilinx FPGA tool sets. • Designing for high More ❯

have Experience of designing FPGA IP cores or sub-systems. Designing FPGA architectures from a technical specification. Design with AMD/Intel FPGA and CPLD devices. Using VHDL/Verilog HDL languages for FPGA design. Implementing high speed, multi-frequency clocking architectures. Designing (code entry to timing analysis) using Intel and/or Xilinx FPGA tool sets. Designing for high More ❯