2 of 2 Part-Time Verilog Jobs

bring some, or all, of the following: Experience in design techniques using VHDL Experience in verification techniques using either VHDL or System Verilog/UVM. Experience in specifying timing and area constraints for efficient FPGA place and route. Ability to analyse system level requirements and derive detailed firmware requirements. Degree ...

desirable if you had: Experience of auto-generated code using model driven engineering using MATLAB and Simulink tools. Experience of design tools such as Verilog, System Verilog and UVM. Experience within the defence industry. What we need from you: Personal attributes and values are just as important ...