2 of 2 UVM Jobs in Berkshire

verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh, TCL, Make, Perl Power aware ...

random test bench development. Familiarity with SerDes and high-level protocols (e.g., PCle, USB, DP) would be advantageous. Extensive digital verification background with some UVM experience. If this role is of any interest please apply directly on LinkedIn or send a copy of your CV to nh@eu-recruit.com. ...