16 of 16 UVM Jobs in the South East

hardware. Proficient with configuration management tools. Experience with Microchip devices and Libero for design synthesis (advantage). Experience verifying HDL using ModelSim or Questasim (UVM beneficial). Desirable Skills - Requirements analysis and management (e.g., DOORS). Experience with SmartFusion, PolarFire or Igloo devices. Knowledge of PCIe NVMe implementations in FPGA. ...

control Experience developing HDL solutions for Microchip devices and using Libero for design synthesis an advantage. Experience verifying HDL solutions using Modelsim/Questasim (UVM experience would be beneficial). UK citizenship What will help you on the job Requirement's analysis, capture and management using DOORs Use of SmartFusion ...

following: Designing complex FPGA architectures using VHDL, Simulink, etc. Targeting Xilinx, Intel, and Microsemi devices Verifying FPGA designs with VHDL & SystemVerilog/UVM Experience with FPGA toolsets and Mentor tools (QuestaSim/ModelSim) Generating low‐level C software for test and integration Confident documenting and configuring designs to a high ...

Strong knowledge of industry-standard EDA simulation and synthesis tools Experience delivering complex, integrated digital designs Additional experience with 5G, communications/DSP algorithms, UVM, AMBA, SystemC/C++, PCIe, JESD, Python or AMD/Xilinx FPGA technology would be highly advantageous. If you're an experienced digital design engineer ...

speed, high‐throughput digital hardware or DSP implementations Timing closure, synthesis and hardware optimisation Complex FPGA or ASIC development projects Experience with wireless communications, UVM, Python or AMBA would be advantageous, but isn’t essential. Why join? Because opportunities like this don’t come along very often. ...

design and verification of FPGA test benches and contribute to robust control systems for quantum hardware. You will own verification environments (SystemVerilog/UVM), drive constrained‐random testing and coverage, and help shape automated regression and CI pipelines. Hybrid work and competitive compensation are offered. #J-18808-Ljbffr ...

## VHDL FPGA Firmware EngineerApplylocations: GB - Southampton: GB - Bristol - Coldharbour Lanetime type: Full timeposted on: Posted Todayjob requisition id: R0026952**Job Description:****Salary Ranges**Engineer: £38k - £53kSenior: £45k - £61kLeonardo UK operates a grade-based salary ...

improved. What They're Looking For Experience managing or leading digital verification engineers Strong background in the verification of complex ICs Strong SystemVerilog and UVM experience, with knowledge of assertions and coverage-driven verification Experience developing verification strategies and using metrics such as code and functional coverage Ability to support ...

customers during presales and product development Oversee the implementation of designs targeting both FPGA and ASIC using industry standard techniques, including the creation of UVM based testbenches Lead AccelerComm's engineering methodology, processes, and design techniques, integrating AI where possible. Nurture professional growth of team members through regular mentoring, coaching … including agile and waterfall, requirements capture and traceability. Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming) Understanding of UVM verification techniques or practical experience using UVM for IP verification Experience with high speed interfaces on and off chip such as AMBA ...

opportunities both for engineers looking to broaden their skills across the full lifecycle and for those who want to specialise in areas such as UVM-based verification. As a Verification Engineer, you will join an industry-leading SoC development team tackling complex design challenges including high-speed interfaces, high-performance … Master's degree in Electronic Engineering (or related field)Experience in digital ASIC design and verification, including: Defining functional requirements for verification environments & metricsSystemVerilog UVM testbenchesFormal proof verificationUnderstanding of C test cases and C codeScripting languages (e.g. Python, Perl, TCL)Desirable skillsExperience with formal verification tools (JasperGold, VC Formal)Familiarity ...

edge verification methodologiesContribute to and Influence the decisions on methodologies/strategies to be adopted for design verification. Develop testbench architectures and develop using UVM or Formal based verification approaches. Define verification-plans, functional coverage, tests and verification methodology for block/chip-level verification. Work with the design team …/Processor subsystems/Formal verificationExpert in developing unit and SoC level test benches using UVM. Integrate the block testbench in chip-level UVM environment and verify integration. Excellent debugging and analytical skills. Proficiency in scripting languages and utilities including Makefile, Python, TCL/tsh, Perl etc.10-15 years ...

algorithms, working across IP development, integration and verification. To support this work, we are looking for a Senior Verification Engineer to support the complete UVM verification of Accelercomm IP. Responsible for verification of RTL implementations for advanced wireless communications IP and modem subsystems, ensuring designs meet functional, performance and quality … requirements prior to FPGA deployment and ASIC tape-out. Key Responsibilities Develop verification plans from design and architecture specifications. Create and maintain SystemVerilog/UVM verification environments. Develop testbenches, assertions, scoreboards and coverage models. Execute directed and constrained-random verification. Analyse coverage and debug RTL and verification issues. Support subsystem ...

Senior Verification Engineer to join a specialist RTL team developing advanced communications technology across ASIC and FPGA platforms. You'll take responsibility for the UVM verification of complex wireless communications IP and modem subsystems, ensuring designs meet functional, performance, and quality requirements ahead of FPGA deployment and ASIC tape-out. … Electronic Engineering, Computer Engineering, or a related discipline. At least 3 years' experience verifying digital ASIC and/or FPGA designs. Strong SystemVerilog and UVM experience. Good understanding of RTL design principles and hardware implementation. Experience with coverage-driven and assertion-based verification. Linux proficiency with Python, Tcl or Bash ...

architect, and develop critical simulation infrastructure, contributing directly to the success of the FPGA team. Key responsibilities include Architect, develop, and maintain advanced UVM/SystemVerilog verification environments for complex FPGA designs. Define and execute comprehensive verification plans, including constrained‐random testing, functional coverage, and code coverage analysis. Collaborate with … strategies, and work collaboratively across design teams to ensure high‐quality outcomes. You'd be a great fit with Strong proficiency in SystemVerilog and UVM for architecting advanced verification environments. Experience using Python for test automation and scripting. Demonstrated ability to lead requirements gathering and define verification plans for complex ...

seeks a Senior Verification Engineer to drive full lifecycle verification of RTL IP across ASIC/FPGA; you will develop verification plans, create UVM testbenches and support integration and tape-out readiness. Requirements include 3+ years in digital verification, strong SystemVerilog/UVM, Linux scripting and a collaborative mindset. Hybrid ...

activities: demos, technical evaluations, benchmarks, methodology guidance Improve customer verification flows and testbench architectures Debug RTL/gate‐level simulation issues and SystemVerilog/UVM environments Analyse functional and code coverage Develop and debug SystemVerilog assertions Collaborate with Sales to grow adoption and identify new opportunities Act as the technical … voice of the customer to R&D What You’ll Need: Typically requires 8–13 yearsof relevant experience Strong knowledge ofVerilog/SystemVerilog, UVM, coverage, and assertions Experience in customer interaction, pre‐sales, or technical support is a plus Strong problem‐solving and communication skills Bachelor’s degree inComputer Engineering ...