Senior Design Verification Engineer
- Hiring Organisation
- Berkeley Square - Talent Specialists in IT & Engineering
- Location
- City of London, London, United Kingdom
3+ years’ experience in FPGA or ASIC functional verification Strong SystemVerilog skills (UVM or similar frameworks) Experience with functional and code coverage Proficiency in Python ; C++ a plus Comfortable working in a Linux environment Familiarity with Verilator and/or Cocotb is advantageous Degree in Electrical Engineering, Computer Science ...