1 of 1 UVM Jobs in Central London

Synthesis, timing constraints development, Lint , CDC checks Understanding of SoC interfaces like QSPI, UART, GPIOs Capable of working with multiple IP vendors and other IP teams Strong experience with UVM based verification, setting up co-simulation environments with ARM CPU models Job Responsibilities: Work on HVL (UVM/SystemVerilog/OVM), C/C++, Perl, TCL programming/scripting skills … verification methodologies and flows. Perform constraint random verification, assertion writing, coverage analysis, debugging. Work with ARM cores, formal verification, SV DPI-C. Experience with verification tools such as UVM, SystemVerilog, and Verilog Strong understanding of semiconductor design and verification methodologies Experience with AMS/Low Power verification techniques and verifying mixed signal ICs a plus. Good knowledge of EDA tools. More ❯