2 UVM Jobs in London

debug and testing methodologies. Experience of System Verilog for design and/or verification. Experience or knowledge of place and route methodologies. Experience of UVM Experience of C, SystemC, C++, Python, Perl, TCL. For more information and a confidential discussion please contact Rachel Mason. more »

and developing starting up new projects meaning extra contract resources are needed. Skills Matlab/Simulink FPGA Architecture (Xilinx/Ultrascale) System Verilog/UVM Firmware Requirements/Architecture The company is looking to interview over the next week and start you as quickly as possible If interested or any more »