digital team that delivered high speed ASICs containing high‐speed mixed‐signal interfaces (display drivers, image sensors, SerDes, RF SoCs, etc.). Strong command of RTL design (SystemVerilog/Verilog), CDC/RDC, STA, place‐and‐route, power intent (UPF/CPF) and DFT/DFD methodologies. Demonstrated success coordinating multi‐lane data paths, clock distribution and fast‐settling DAC More ❯
City of London, London, United Kingdom Hybrid / WFH Options
Platform Recruitment Limited
tapeout on next-generation chip architectures in areas like memory, interconnect, and high-speed interface design. Key Responsibilities: + Develop and Integrate designs of RTL for digital blocks (using Verilog/SystemVerilog/VHDL) + Undertake Digital IC Design processes & Perform design synthesis, linting + Complete projects from conception to completion Skills Required: + Experience with frontend RTL Design + … Strong Experience with SystemVerilog, Verilog or VHDL + Has had exposure to ASIC design flow (Lint, syntheisis, simulation) + Digital Design Principles experience pipelining, clock domain crossing Further Details: This role offers remote working with a potential visit into the office every month. A competitive salary, bonus scheme, and a strong benefits package. If you are a driven and experienced More ❯
and refined for a specialised edge. You’ll work on designs featuring high-speed serial I/O, PCIe interfaces, and large-scale FPGA deployments. The tooling is standard, (Verilog/SystemVerilog, Verilator, and C++,) what you build needs to be anything but. If the manufacturer thinks it's possible with their hardware, you've not gone far enough. Being More ❯
