4 of 4 SystemVerilog Jobs in the City of London

infrastructure integrated directly into trading, research, and networking pipelines. What You’ll Be Doing Designing and implementing latency-optimised FPGA systems in Verilog/SystemVerilog Developing high-speed modules (PCIe, Ethernet, DDR/QDR) with deep pipelining Using simulation and formal tools (Verilator, Cocotb, etc.) for validation Working across teams ...

boundaries of high-performance IP on next generation FPGA and Adaptive SoC platforms and your experience looks highly relevant. They require someone with strong SystemVerilog RTL capability, confident across 100Gb Ethernet, PCIe Gen5 and AXI, and comfortable taking designs through to timing closure without fuss. Vivado and Vitis are central ...

testbench issues efficiently. At least two years of professional RTL functional verification experience for FPGA or ASIC designs. Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis. Proficiency in Python and/or C++ for building verification infrastructure, tooling, and automation. ...

ASIC Design Engineer Location: London or UK Remote I am seeking an ASIC Design Engineer to join a rapidly growing scale-up at the forefront of hardware security for AIoT. This is a business-critical ...