26 to 50 of 59 Perl Jobs in England

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Guildford, Surrey, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Chesterfield, Derbyshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Peterborough, Cambridgeshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Preston, Lancashire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
High Wycombe, Buckinghamshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Northampton, Northamptonshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Dartford, Kent, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Norwich, Norfolk, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
South London, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Lincoln, Lincolnshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Oxford, Oxfordshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Bedford, Bedfordshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Colchester, Essex, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Reading, Berkshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Bournemouth, Dorset, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Cheltenham, Gloucestershire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Ipswich, Suffolk, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
East Anglia, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Wakefield, West Yorkshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Hemel Hempstead, Hertfordshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Newport, Isle of Wight, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Newcastle upon Tyne, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Hull, East Yorkshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Crawley, West Sussex, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
York, North Yorkshire, UK
Employment Type
Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...