26 to 31 of 31 Field-Programmable-Gate-Array Jobs in London

Do you want to work on some of the most advanced technology in the world? Our client operates one of the most powerful private HPC clusters globally, with 10s of thousands of GPUs (including 1000s ...

verification, and integration teams to design, implement, and optimize IP targeting AMD Adaptive SoCs. Responsibilities include:Developing RTL in SystemVerilog for high-performance FPGA/Adaptive SoC designsImplementing and optimizing high-speed connectivity protocolsCollaborating with cross-functional teams on integration, timing closure, and validationDriving improvements across synthesis, place and route … candidate must meet the following qualifications:A. RTL Design & CodingDeep hands-on experience with SystemVerilog HDL for RTL designProven ability to develop IP targeting FPGA/Adaptive SoC platformsB. High-Speed ProtocolsStrong experience with:100Gb EthernetPCIe Gen5AMBA/AXI interface protocolsC. Adaptive SoC/FPGA ExpertiseIn-depth understanding of FPGA ...

most prestigious high-frequency trading companies in the world to find a verification engineer to help verify their complex low-latency FPGA systems. You'll be joining a team at the forefront of innovation in design verification, where you'll be supported in pushing the envelope alongside top pioneers … analytical capability, able to isolate and resolve complex RTL and testbench issues efficiently. At least two years of professional RTL functional verification experience for FPGA or ASIC designs. Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis. Proficiency in Python ...

most prestigious high-frequency trading companies in the world to find a verification engineer to help verify their complex low-latency FPGA systems. You'll be joining a team at the forefront of innovation in design verification, where you'll be supported in pushing the envelope alongside top pioneers … analytical capability, able to isolate and resolve complex RTL and testbench issues efficiently. At least two years of professional RTL functional verification experience for FPGA or ASIC designs. Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis. Proficiency in Python ...

constrained-random and coverage-driven verificationAutomate regressions using Python scriptingWork within CI/CD environments and version control using GitSupport ASIC/SoC/FPGA verification flowsEssential Skills & ExperienceStrong experience as a Verification Engineer/ASIC Verification EngineerProven UVM and class-based verification expertiseSolid background in DSP verification … signal processing)Python for automation and regressionExperience with SoC/ASIC/FPGA environmentsGit version controlDesirableMATLAB experienceExposure to Vivado/Vitis or adaptive SoC flowsContract role | Market rate | Remote workingIf youre a senior, hands-on verification engineer looking for a challenging DSP-focused contract, apply now or get in touch ...

Location: Northampton, Northamptonshire, East Midlands, UKGreat opportunity for a Formal Verification Engineer with a proven track record of verifying complex FPGA or ASIC designs within the Semiconductor industry. Youll play a key role in an innovative High-Tech company revolutionizing wired connectivity and pushing the boundaries of AI related innovation. … include:Bachelors/Masters Degree in Electronics related discipline.5+ years experience of working within the semiconductor industry.Proven experience in the Verification of complex designs - FPGA or ASIC.Good scripting skills (Python, Perl or TCL for automation).Working with RTL designers to develop a formal micro-architecture specification.In-depth understanding of Formal ...