22 of 22 Verification Engineer Jobs in London

Join to apply for the Digital Design & Verification Engineer – Graduate/Junior role at microTECH Global LTD Join to apply for the Digital Design & Verification Engineer – Graduate/Junior role at microTECH Global LTD Job Title: Digital Design & Verification Engineer – Graduate/Junior Position: Graduates & Junior Location: Hertfordshire Hybrid Salary Range: Negotiable Client Information … We are building a revolutionary RISC-V-based GPU and AI platform, and we’re hiring talented engineers in Hardware Design and Hardware Verification to join us on this mission. If you thrive on innovation and want to work on cutting-edge vector processing and neural compute technologies, this is your opportunity. Job Description Job Title: Digital Design & Verification Engineer – Graduate/Junior Position: Graduates & Junior Type: Contract or Permanent Location: Hertfordshire Hybrid Salary Range: Negotiable Client Information We are building a revolutionary RISC-V-based GPU and AI platform, and we’re hiring talented engineers in Hardware Design and Hardware Verification to join us on this mission. If you thrive on innovation and want to More ❯

within the community. So, what's your possible? Opportunity: This is more than just a job; it's a mission. Salary: £47,400- £67,000 The V&V Principal engineer will support the planning, conduct and reporting of V&V work packages and activities in order to prove our hardware and software product compliance to their associated requirements. The … V&V Principal Engineer will work within multi-disciplined project teams under direction of the project delivery management and V&V leadership to effectively and efficiently deliver the assigned V&V activities. Our UK Defence business is a Sovereign software and systems centre of excellence. As well as developing and supporting UK wide and internationally deployed multi-domain command More ❯

within the community. So, what's your possible? Opportunity: This is more than just a job; it's a mission. Salary: £47,400- £67,000 The V&V Principal engineer will support the planning, conduct and reporting of V&V work packages and activities in order to prove our hardware and software product compliance to their associated requirements. The … V&V Principal Engineer will work within multi-disciplined project teams under direction of the project delivery management and V&V leadership to effectively and efficiently deliver the assigned V&V activities. Our UK Defence business is a Sovereign software and systems centre of excellence. As well as developing and supporting UK wide and internationally deployed multi-domain command More ❯

Join to apply for the Design Verification Engineer role at G-Research Join to apply for the Design Verification Engineer role at G-Research Get AI-powered advice on this job and more exclusive features. Do you want to tackle the biggest questions in finance with near infinite compute power at your fingertips? G-Research is … in our new Soho Place office – opened in 2023 - in the heart of Central London and home to our Research Lab. The role G-Research is seeking a Design Verification Engineer to join our world-class Software Engineering function. As a Design Verification Engineer, you will provide technical expertise, support and guidance around formal verification … test plans, creating test benches and analysing code coverage. Key responsibilities of the role include: Developing System Verilog based VMM/UVM test bench environments Developing assertion based formal verification Developing co-simulation environments to verify between C/C++ models and RTL modules Writing test plans, creating test bench specifications and analysing code coverage plans Implementing constrained-random More ❯

Position: ASIC Verification Engineer Location: Oxfordshire, UK Full time/Perm: Office based & hybrid working arrangement with the option to work from home on Monday and Fridays. About the Client: My client is one of the leading providers of high-performance client, data centre and enterprise solid-state storage products that enables customers to tackle storage challenges head … with cross functional teams including architecture, firmware and validation. Essential qualifications and skills: - Bachelor or Master’s degree in Electronic Engineering or related field - 12+ years of digital ASIC verification experience - Practical experience and understanding of: - Requirement capture, verification planning and coverage closure - System Verilog and UVM test benches - Creation of UVM test benches - System Verilog assertions - Managing More ❯

ex-Apple, ARM and Huawei talent, offering full technical freedom, rare foundry access, and long-term stability in a low-politics, high-impact environment. They're hiring a Senior Verification Engineer to help build their verification infrastructure. Responsibilities Implement verification infrastructure and test cases in collaboration with the design team and external partners. Debug failures, create … and track issues to resolution. Develop and maintain automated regression test infrastructure and gatekeepers. Requirements Deep expertise in industry-standard verification methodologies, including proficiency with SystemVerilog and UVM. Experience with GPUs/CPUs is highly desirable. Demonstrated ability to collaborate effectively with design teams to meet objectives. If you'd like more information, apply below More ❯

Job Title: Hardware Design and Verification Engineer Position: Junior - Mid level Engineers Type: Contract or Permanent Location: Hertfordshire Hybrid Salary Range: Negotiable Client Information: We are building a revolutionary RISC-V-based GPU and AI platform, and we're hiring talented engineers in Hardware Design and Hardware Verification to join us on this mission. If you thrive … V vector core GPU Design high-performance, power-efficient compute units for graphics and AI workloads Optimize microarchitecture to meet performance, power, and area (PPA) targets Work collaboratively with verification teams to ensure correctness and efficiency Participate in design reviews and contribute to technical decision-making Document technical specifications and development progress Contribute to bring-up, synthesis, and physical … aware design flows Verification Responsibilities: Develop UVM/SystemVerilog testbenches and functional verification plans Implement directed and constrained-random tests for robust coverage Execute regression testing, debug RTL, and track issues to resolution Verify block-level and system-level behavior for our GPU and AI IPs Utilize formal verification techniques when applicable Measure and validate system performance More ❯

spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators. These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing … redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb. FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing … real-time environment. No financial experience is necessary. Responsibilities Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment Writing detailed verification plans Quickly root-cause RTL bugs Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs Managing test suites and continuous integration infrastructure Developing More ❯

Social network you want to login/join with: Design Verification Engineer, south west london Client: ALOIS Solutions Location: south west london, United Kingdom Job Category: Other - EU work permit required: Yes Job Views: 1 Posted: 31.05.2025 Expiry Date: 15.07.2025 Job Description: Verify CPU connectivity to IP blocks (using ASM boot , and C code, GNU toolchain ) The tasks … will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs/Subsystems Run regressions, debug test failures and file bug reports as needed. Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of … coverage gaps. Provide verification reports to demonstrate all implemented tests pass on the RTL. Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases. #J-18808-Ljbffr More ❯

Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs … test failures and file bug report as needed. • Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps. • Provide verification report as needed to show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal More ❯

Experienced AMS Design Verification Engineer (m/f/d) At Apple, we work daily to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and creative Design Verification Engineer. As a member … products that will delight and encourage millions of Apple's customers every single day. Do your life's best work here at Apple! This role is for a Design Verification engineer who will enable bug-free first silicon for the mixed-signal designs in our Munich team. The responsibilities include all phases of pre-silicon verification including … but not limited to: construction of verification environments, coding of test scenarios and assertions and close collaboration with Analog and Digital Design engineers. Description Definition and design of Self-checking verification environments for multi-layer systems using the SystemVerilog UVM library. The responsibility spans from concept discussions, verification strategy definition and execution of the verification tasks More ❯

A leading quantitative trading firm is looking for a Senior FPGA Test & Verification Engineer to join their core hardware engineering team. This group is responsible for building and validating high-performance FPGA-based trading systems used across global financial markets. This is an opportunity to work on low-latency infrastructure at the forefront of electronic trading, alongside experts … in hardware, software, and quantitative research. Key Responsibilities: Develop and lead testing and verification strategies for FPGA systems Define best practices and maintain testing standards across projects Implement simulation environments and hardware-in-the-loop testing Collaborate closely with trading and engineering teams to ensure robust, reliable systems Key Requirements: Strong experience in functional verification, including coverage models More ❯

A leading quantitative trading firm is looking for a Senior FPGA Test & Verification Engineer to join their core hardware engineering team. This group is responsible for building and validating high-performance FPGA-based trading systems used across global financial markets. This is an opportunity to work on low-latency infrastructure at the forefront of electronic trading, alongside experts … in hardware, software, and quantitative research. Key Responsibilities: Develop and lead testing and verification strategies for FPGA systems Define best practices and maintain testing standards across projects Implement simulation environments and hardware-in-the-loop testing Collaborate closely with trading and engineering teams to ensure robust, reliable systems Key Requirements: Strong experience in functional verification, including coverage models More ❯

Location: Remote/Onsite (We are looking for candidates who are currently based in Europe and are open to working remotely.) Job Overview: We are seeking a proficient SoC Verification Engineer with a strong background in ARM-based system designs and verification methodologies. The ideal candidate will be experienced in verifying complex SoC architectures, utilizing languages such … as C, System Verilog (SV), and Universal Verification Methodology (UVM). This role involves close collaboration with design teams to ensure that all aspects of the SoC are thoroughly validated, from architectural design to implementation. The candidate will also contribute to the development of verification plans, testbenches, and methodologies to enhance overall product quality. Key Responsibilities: Develop and … implement verification testbenches and components for ARM-based SoC designs. Execute thorough verification processes, including the development of test plans and test cases using C, SV, and UVM. Collaborate closely with design teams to understand and validate the various features of the SoC. Focus on stress testing, bug identification, and overall quality improvement of SoC IPs. Provide clear More ❯

to design and procurement of the space segment, ground segment and user infrastructure to provide communications services by the end of the decade. We are seeking a systems-oriented engineer to lead the integration, verification, validation (IVV), and operational readiness of a complex satellite communications system. You will ensure alignment from satellite manufacture through to ground operations and … service delivery, with a focus on the entire end-to-end chain. The day-to-day • Define and implement a comprehensive end-to-end communications verification strategy across terminal, ground, and space segments. Lead the development and execution of the system-level IVV roadmap for the communications service. • Design and implement an end-to-end communications test bed, identifying … and engaging industry partners as needed. • Own the test lifecycle, including defining verification methods, maintaining Verification Control Matrices (VCMs) and Documents (VCDs), generating Test Plans, Test Procedures, and issuing Test Reports. • Support the planning and execution of Satellite Validation Tests (SVT), including simulation campaigns and operations command/telemetry validation. • Contribute to the planning and definition of System More ❯

our news pages to learn more about this and other Quantinuum scientific breakthroughs and achievements: https://www.quantinuum.com/news We are looking for a FPGA Design and Verification Engineer to design, simulate, and verify FPGA functionality for the electronic control systems that drive our next-generation quantum computers at our Broomfield, CO location. For this role … components, and other low-speed peripherals and sensors. Key Responsibilities: Develop a complex electronic control system capable of controlling digital, analog, and RF signals Perform FPGA design, simulation, and verification Collaborate with PCB designers, software, and other engineers to complete projects on-time with first-pass success Provide technical expertise that informs future product development and process improvements across … in Electrical Engineering or related field 10+ years of experience in the specification, development, and validation of complex electronic products Demonstrated technical excellence and leadership in FPGA design and verification, including Xilinx software and IP, as well as mastery of System Verilog, Verilog, and VHDL Verification and simulation experience with QuestaSim, QVIP, and related tools Embedded software experience More ❯

Engineering General Summary: About the role Are you interested in working with a world-class CPU design team? Are you interested in the application of formal methods to the verification of application processors? In contributing to the development of the next generation of formal methodologies in this space? The Qualcomm CPU team has some of the best CPU architects … and engineers on the planet, developing the processors that will power the future. Come and join us on this exciting adventure. Sharpen your formal verification skills to their fullest on some of the complex designs ever attempted. Roles and Responsibilities Work with design team to understand design intent and bring up verification plans and schedules with an eye … towards the end-to-end formalisation of the refinement from architecture to micro-architecture. Define formal verification architecture, develop test plans and build end-to-end formal sign-off environments for Qualcomm CPU components. Engage in full-spectrum deployment of model-checking technology to hardware designs including property verification , math proofs, architectural modelling and validation amongst other cutting More ❯

Add to Favorites Design Verification Engineer Do your life’s best work here - with the whole world watching. Join a rapidly growing team at our UK GPU design centre. At Apple, new ideas and complex challenges have a way of becoming phenomenal products, services, and customer experiences very quickly. The Design Verification Engineer will be responsible … for the pre-silicon RTL verification of blocks in low power embedded graphics cores. This includes deep understanding of the micro-architectural details of their block and how it works within the broader GPU design. A strong computer architecture background, preferably in graphics, and a strong foundation in verification methodology will be used to close testing coverage with … high confidence. Description Use SystemVerilog, UVM and C++ with industry leading simulation tools and methodologies to verify complex GPU designs. Develop verification plans in coordination with design leads and architects. Create and maintain verification test bench components and environments. Generate directed and directed random tests. Run simulations and debug design and environment issues. Build functional coverage points, analyze More ❯

Social network you want to login/join with: Design Verification Engineer, london (city of london) col-narrow-left Client: IC Resources Location: london (city of london), United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 2 Posted: 16.06.2025 Expiry Date: 31.07.2025 col-wide Job Description: Work on cutting edge designs within … a prestigious group! I am seeking a GPU Verification Engineer to join my clients growing GPU Division. This position is a unique opportunity to exercise your hardware verification skills on cutting edge designs within their prestigious Graphics group. Here you will exercise your skills on key components that meet latest demands and improvements for graphics, AI or … will spend your time creating the graphics and AI chips that are at the core of your favourite electronic products. You will: Be responsible for the delivery of all verification activities related to a GPU component or sub-system from early stages of verification planning to sign-off Create verification plans, develop and maintain UVM testbench components More ❯

Social network you want to login/join with: Work on cutting edge designs within a prestigious group! I am seeking a GPU Verification Engineer to join my clients growing GPU Division. This position is a unique opportunity to exercise your hardware verification skills on cutting edge designs within their prestigious Graphics group. Here you will exercise … will spend your time creating the graphics and AI chips that are at the core of your favourite electronic products. You will: Be responsible for the delivery of all verification activities related to a GPU component or sub-system from early stages of verification planning to sign-off. Create verification plans, develop and maintain UVM testbench components. … Participate in all stages of design specification definition providing feedback from the verification perspective. Develop testbenches in UVM, write tests, sequences, functional coverage, assertions & verification plans. Be responsible for the definition, effort estimation and tracking of your own work. Be able to influence and advance our GPU verification methodology. Have the opportunity to lead, coach and mentor More ❯

GPU Design Verification Engineer, London Client: ic resources Location: London, United Kingdom Job Category: Other EU work permit required: Yes Job Reference: 7ef826e48f70 Job Views: 4 Posted: 02.06.2025 Expiry Date: 17.07.2025 Job Description: GPU UK Division - Senior and Principal Verification Engineers Work on cutting-edge designs within a prestigious group, with locations in Bristol, Cambridge, London outskirts … and Manchester. I am seeking Senior and Principal level Verification Engineers to join my client's growing GPU Division. This is a unique opportunity to utilize your hardware verification skills on innovative designs within the PowerVR Hardware Graphics group. You will work on key components that address the latest demands in graphics, AI, connectivity processors, and related IP. … to a company that creates graphics and AI chips central to electronic products, expanding their IP portfolio to include RISC-V CPUs to enhance their Compute offerings. Responsibilities: Deliver verification activities for GPU components or sub-systems from planning to sign-off. Create verification plans, develop and maintain UVM testbench components. Participate in design specification stages, providing verification More ❯

About us: Axiomise is the world’s only formal verification (FV) training, consulting, services and custom solutions company. In its 8th year, we have delivered training to over a hundred engineers globally and provided our consulting & services to some of the best names in the semiconductor industry. We designed the industry’s first and only vendor-neutral fully automated … RISC-V formal verification app that has been used to find bugs in pre-existing processors and exhaustively prove bug absence. We love formal methods, and we use them day and night to sign-off designs, so our customers do not leave bugs in silicon. Snapshot of our culture: We do not have a hierarchical structure so you will … customer and employee needs. About the Job: We are looking to hire top-notch engineering talent for the UK. Your typical day job would involve building cutting-edge formal verification testbench environments to find bugs and build proofs of bug absence in SoCs containing processors, video/GPUs, networking, AI/ML designs. Formal verification is the only More ❯