SystemVerilog Jobs in the Midlands

101 to 125 of 138 SystemVerilog Jobs in the Midlands

Design Verification Engineer

worcester, midlands, United Kingdom
Hybrid / WFH Options
Athsai
As The Lead/Engineer - Design Verification , you will work with Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it More ❯
Posted:

Design Verification Engineer

leicester, midlands, United Kingdom
Hybrid / WFH Options
Athsai
As The Lead/Engineer - Design Verification , you will work with Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it More ❯
Posted:

Design Verification Engineer

nottingham, midlands, United Kingdom
Hybrid / WFH Options
Athsai
As The Lead/Engineer - Design Verification , you will work with Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it More ❯
Posted:

Design Verification Engineer

birmingham, midlands, United Kingdom
Hybrid / WFH Options
Athsai
As The Lead/Engineer - Design Verification , you will work with Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it More ❯
Posted:

Design Verification Engineer

stoke-on-trent, midlands, United Kingdom
Hybrid / WFH Options
Athsai
As The Lead/Engineer - Design Verification , you will work with Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it More ❯
Posted:

Design Verification Engineer

coventry, midlands, United Kingdom
Hybrid / WFH Options
Athsai
As The Lead/Engineer - Design Verification , you will work with Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it More ❯
Posted:

Design Verification Engineer

northampton, midlands, United Kingdom
Hybrid / WFH Options
Athsai
As The Lead/Engineer - Design Verification , you will work with Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it More ❯
Posted:

Design Verification Engineer

derby, midlands, United Kingdom
Hybrid / WFH Options
Athsai
As The Lead/Engineer - Design Verification , you will work with Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it More ❯
Posted:

System-on-Chip Design Engineer

shrewsbury, midlands, United Kingdom
Skywaves Rise
Required Skills & Knowledge: Micro-architecture design RTL coding in System Verilog for aviation project Synthesis using Design Compiler/Fusion compiler 5 years SDC development LEC failure debugs RTL/gate level debug experience using tools such as Verdi More ❯
Posted:

System-on-Chip Design Engineer

birmingham, midlands, United Kingdom
Skywaves Rise
Required Skills & Knowledge: Micro-architecture design RTL coding in System Verilog for aviation project Synthesis using Design Compiler/Fusion compiler 5 years SDC development LEC failure debugs RTL/gate level debug experience using tools such as Verdi More ❯
Posted:

System-on-Chip Design Engineer

worcester, midlands, United Kingdom
Skywaves Rise
Required Skills & Knowledge: Micro-architecture design RTL coding in System Verilog for aviation project Synthesis using Design Compiler/Fusion compiler 5 years SDC development LEC failure debugs RTL/gate level debug experience using tools such as Verdi More ❯
Posted:

System-on-Chip Design Engineer

chesterfield, midlands, United Kingdom
Skywaves Rise
Required Skills & Knowledge: Micro-architecture design RTL coding in System Verilog for aviation project Synthesis using Design Compiler/Fusion compiler 5 years SDC development LEC failure debugs RTL/gate level debug experience using tools such as Verdi More ❯
Posted:

System-on-Chip Design Engineer

telford, midlands, United Kingdom
Skywaves Rise
Required Skills & Knowledge: Micro-architecture design RTL coding in System Verilog for aviation project Synthesis using Design Compiler/Fusion compiler 5 years SDC development LEC failure debugs RTL/gate level debug experience using tools such as Verdi More ❯
Posted:

System-on-Chip Design Engineer

wolverhampton, midlands, United Kingdom
Skywaves Rise
Required Skills & Knowledge: Micro-architecture design RTL coding in System Verilog for aviation project Synthesis using Design Compiler/Fusion compiler 5 years SDC development LEC failure debugs RTL/gate level debug experience using tools such as Verdi More ❯
Posted:

System-on-Chip Design Engineer

west midlands, midlands, United Kingdom
Skywaves Rise
Required Skills & Knowledge: Micro-architecture design RTL coding in System Verilog for aviation project Synthesis using Design Compiler/Fusion compiler 5 years SDC development LEC failure debugs RTL/gate level debug experience using tools such as Verdi More ❯
Posted:

System-on-Chip Design Engineer

newport, midlands, United Kingdom
Skywaves Rise
Required Skills & Knowledge: Micro-architecture design RTL coding in System Verilog for aviation project Synthesis using Design Compiler/Fusion compiler 5 years SDC development LEC failure debugs RTL/gate level debug experience using tools such as Verdi More ❯
Posted:

System-on-Chip Design Engineer

lincoln, midlands, United Kingdom
Skywaves Rise
Required Skills & Knowledge: Micro-architecture design RTL coding in System Verilog for aviation project Synthesis using Design Compiler/Fusion compiler 5 years SDC development LEC failure debugs RTL/gate level debug experience using tools such as Verdi More ❯
Posted:

System-on-Chip Design Engineer

coventry, midlands, United Kingdom
Skywaves Rise
Required Skills & Knowledge: Micro-architecture design RTL coding in System Verilog for aviation project Synthesis using Design Compiler/Fusion compiler 5 years SDC development LEC failure debugs RTL/gate level debug experience using tools such as Verdi More ❯
Posted:

System-on-Chip Design Engineer

northampton, midlands, United Kingdom
Skywaves Rise
Required Skills & Knowledge: Micro-architecture design RTL coding in System Verilog for aviation project Synthesis using Design Compiler/Fusion compiler 5 years SDC development LEC failure debugs RTL/gate level debug experience using tools such as Verdi More ❯
Posted:

System-on-Chip Design Engineer

derby, midlands, United Kingdom
Skywaves Rise
Required Skills & Knowledge: Micro-architecture design RTL coding in System Verilog for aviation project Synthesis using Design Compiler/Fusion compiler 5 years SDC development LEC failure debugs RTL/gate level debug experience using tools such as Verdi More ❯
Posted:

System-on-Chip Design Engineer

stoke-on-trent, midlands, United Kingdom
Skywaves Rise
Required Skills & Knowledge: Micro-architecture design RTL coding in System Verilog for aviation project Synthesis using Design Compiler/Fusion compiler 5 years SDC development LEC failure debugs RTL/gate level debug experience using tools such as Verdi More ❯
Posted:

System-on-Chip Design Engineer

nottingham, midlands, United Kingdom
Skywaves Rise
Required Skills & Knowledge: Micro-architecture design RTL coding in System Verilog for aviation project Synthesis using Design Compiler/Fusion compiler 5 years SDC development LEC failure debugs RTL/gate level debug experience using tools such as Verdi More ❯
Posted:

System-on-Chip Design Engineer

leicester, midlands, United Kingdom
Skywaves Rise
Required Skills & Knowledge: Micro-architecture design RTL coding in System Verilog for aviation project Synthesis using Design Compiler/Fusion compiler 5 years SDC development LEC failure debugs RTL/gate level debug experience using tools such as Verdi More ❯
Posted:

RTL Design/Lead

worcester, midlands, united kingdom
Stackstudio Digital Ltd
Role - RTL Design/LeadLocation:EU/Remote Mandatory Skill: SoC Integrtion, IP integration RTL design & Coding RTL lint, RTL CDC Verilog/System Verilog Industry Experience : 5 to 10 years SoC Design engineer with experience working on SOCs based More ❯
Posted:

RTL Design/Lead

wolverhampton, midlands, united kingdom
Stackstudio Digital Ltd
Role - RTL Design/LeadLocation:EU/Remote Mandatory Skill: SoC Integrtion, IP integration RTL design & Coding RTL lint, RTL CDC Verilog/System Verilog Industry Experience : 5 to 10 years SoC Design engineer with experience working on SOCs based More ❯
Posted: