16 of 16 ASIC Jobs in Midlothian

correlation to simulationContribute to methodology improvements and automation initiativesMinimum Qualifications:BS in Electrical or Computer Engineering (or equivalent)4+ years of experience in ASIC/SoC digital designProficiency in Verilog/SystemVerilog and scripting languages (Python, C)Familiarity with RTL-to-GDS flows (e.g., Genus, Innovus, Tempus, Conformal)Understanding ...

coverage analysis, and test development. Drive continuous improvement of verification processes through scripting, automation, and emerging AI technologies. PREFERRED EXPERIENCE: Proficient in IP-level ASIC verification. Strong experience with UVM testbenches and SystemVerilog. Proficient in debugging RTL and firmware using industry-standard simulation tools. Experience with Verilog, SystemVerilog ...

environment and verify integration.Excellent debugging and analytical skills.Proficiency in scripting languages and utilities including Makefile, Python, TCL/tsh, Perl etc.10-15 years in ASIC design verification.Additional Preferred QualificationsExperience with HW emulation or FPGA prototypingLow power methodologies , e.g. UPFExperience in behavioural modelling of analogue circuitsExperience in verifying processor based designsKnowledge ...

debug; correlate physical design decisions with lab measurementsMinimum Qualifications:BS in Electrical or Computer Engineering (or equivalent)4+ years of experience in ASIC/SoC physical design and implementationStrong proficiency with Cadence digital implementation tools (Genus, Innovus, Tempus, Conformal, Voltus, Pegasus)Solid understanding of static timing analysis, clock domain crossing ...

ensure a fully specified, verified and correctly implemented design.Contribute to product definition, prototype evaluation, test development and product release to ensure that the ASIC can be manufactured, is competitive and meets the customers’ requirements. Participate in project meetings and design reviews.Required Skills and Qualifications: Bachelor’s, Master ...

brands. They seek a Staff AMS Verification Engineer to be responsible for ensuring the functional correctness and robustness of complex analog and mixed-signal ASIC designs through advanced verification methodologies. Working closely with architects, designers, DFT, and the verification team, you will deliver high-quality silicon solutions and enjoy ...

Work closely with cross-functional engineering teams Help improve verification methodology and best practice About You You'll ideally have experience with: SystemVerilog UVM ASIC or SoC Verification Functional Coverage SystemVerilog Assertions (SVA) RTL Debug Verification Planning Experience within automotive or safety-critical semiconductor development would be beneficial ...

Networking Technology & Solutions IP Group at AMD is expanding its Data Centre design teams in Edinburgh and Belfast. We architect and deliver high-performance ASIC solutions for next-generation data center networking, enabling large-scale AI training and inference clusters. Our work spans the full development lifecycle — from architecture definition … impacts real-world workloads. About the Role: As a senior member of the design team, you will: Lead the design and delivery of complex ASIC blocks for data center networking silicon Contribute to and influence architecture definition and microarchitecture decisions Translate system requirements into detailed specifications and high-quality ...

hardware development team. In this role, you will be responsible for ensuring the functional correctness and robustness of complex digital and mixed-signal ASIC designs through advanced verification methodologies. You will work closely with architects, designers, and other verification engineers to deliver high-quality silicon solutions.ResponsibilitiesDevelop and execute comprehensive verification … plans for complex mixed-signal ASIC designs.Create and maintain testbenches using SystemVerilog/UVM.Write and debug test cases to verify functionality, performance, and corner cases.Perform block-level and full-chip verification, including simulation, coverage analysis, and regression run/debug.Collaborate with design engineers to understand specifications and identify verification requirements.Analyze ...

offer a unique environment where contribution is heavily rewarded! This role is based in either our Newbury or Edinburgh office.Key Responsibilities: Assist in the ASIC product development and test processPort ASIC RTL code onto FPGA with minimal changes ready for pre-Si testingPort systems onto FPGAs to test Proof … construct an automated regression test for the complete design.Contribute to product definition, prototype evaluation, test development & product release to ensure that the ASIC will meet the customers’ requirementsParticipate in project meetings and reviewsRequired Skills and Qualifications: Master’s/Bachelor’s degree (and/or equivalent) and background in Electronics ...

optimize test time. Own the development of production-ready hardware, including probe cards and loadboards. Develop robust ATE-level characterization solutions to validate key ASIC parameters. Automotive Qualification: Develop and implement robust automotive qualification plans for SPAD ICs, ensuring compliance with industry standards and relevant regulatory requirements (e.g. … ensure traceability. Direct failure analysis initiatives to identify and resolve potential manufacturing or process issues effectively.Cross-Functional Collaboration: Engage with both system-level and ASIC-level teams to ensure effective communication and mutual understanding of product requirements. Facilitate technical discussions and collaborations to drive key project milestones and ensure alignment ...

faced by today’s five billion mobile subscribers and finally bring broadband to the billions who remain unconnected.Position OverviewWe are seeking a SoC/ASIC Architect.The Silicon Team in Edinburgh is a small, highly focused group responsible for developing high‐value silicon that is core to AST’s mission ...

move to the UK. In this role, you’ll be responsible for ensuring the functional correctness and robustness of complex digital and mixed-signal ASIC designs using advanced verification methodologies. Key responsibilities Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs Create and maintain UVM-based SystemVerilog … verification Strong proficiency in SystemVerilog, UVM, and leading simulation tools (e.g., Synopsys VCS, Cadence Xcelium) Solid understanding of digital design principles, RTL design, and ASIC development flows Experience with scripting languages (Python, Perl, Shell, etc.) Familiarity with formal verification, assertion-based verification, and coverage-driven verification techniques Excellent problem-solving ...

connectivity gaps faced by today’s five billion mobile subscribers and finally bring broadband to the billions who remain unconnected.Position OverviewWe are seeking an ASIC Design Engineer to contribute to the design and implementation of complex silicon solutions used in AST’s space‐based communications systems.The Silicon Team in Edinburgh … close collaboration across engineering disciplines. You will work alongside architecture, verification, and system teams—both internal and external—to deliver robust, high‐performance ASIC and SoC designs from concept through tape‐out.Key Responsibilities:• Create high‐quality micro‐architecture specifications and RTL code.• Contribute to SoC integration and subsystem development.• Work ...

with an ability to work independently and as part of a wider design team.Responsibilities: All aspects of RTL to GDS2 physical implementation for complex ASIC projects.Working with Digital Design, Analogue Layout and DFT teams to ensure on time and high-quality results.Participating in project scoping and planning activities.Developing … ideal candidate should be familiar with: Synopsys Design Compiler and PrimetimeCadence Innovus, Voltus and ConformalHands-on working knowledge of deep sub-micron ASIC implementation and expertise in areas such as: RTL synthesisTiming constraint debug and developmentFloorplanning and power planningClock tree synthesisP&R optimisation, timing closure and ECO implementationStatic timing analysisLogical ...

design verification background (digital or mixed-signal) Experience leading small teams or projects Skills in SystemVerilog, UVM, assertions, coverage Exposure to mixed-signal/ASIC environments (RNM a bonus) Why join Work on globally deployed technology Clear path into technical leadership Relocation support available High-impact role in a growing ...