5 of 5 SystemVerilog Jobs in the North West

FPGA Engineers

Hiring Organisation
Defence
Location
Stockport, Greater Manchester, UK
most of the following: Designing complex FPGA architectures using VHDL, Simulink, etc. Targeting Xilinx, Intel, and Microsemi devices Verifying FPGA designs with VHDL & SystemVerilog/UVM Experience with FPGA toolsets and Mentor tools (QuestaSim/ModelSim) Generating low-level C software for test and integration Confident documenting and configuring designs ...

Principal Design Engineer

Location
Manchester, England, United Kingdom
development Experience in static design checks, including CDC, RDC, X-prop, Lint and UPF static checks Experience creating design specifications Experience with Verilog/SystemVerilog and verification methodologies Strong delivery record of sophisticated RTL subsystems in reasonable timescales Ability to navigate and make high-level analysis driven PPA trade-offs ...

Postdoc: Edge Vision Processor Architect (FPGA/RTL)

Location
Manchester, England, United Kingdom
vision processor hardware, with a focus on near-sensor integration for advanced edge computing scenarios. The role covers RTL-level design using Verilog/SystemVerilog or VHDL, with FPGA implementations and potential ASIC work, plus system modelling and hardware-software co-design and sensor interfacing. #J-18808-Ljbffr ...

Postdoctoral Research Associate in Digital Design

Location
Manchester, England, United Kingdom
with potential for future ASIC implementation. You will carry out system modelling, design novel parallel processor architectures at the RTL level (using Verilog/SystemVerilog or VHDL), and drive the hardware-software co-design aspects of these new architectures. Additionally, the role involves interfacing with high-speed sensors and building ...

Senior Verification Engineer - Media IP

Location
Manchester, England, United Kingdom
early planning through sign-off. Contribute to the overall DPU verification architecture, planning, integration strategy and quality criteria. Architect reusable, scalable and high-performance SystemVerilog/UVM environments and verification IP. Define verification plans, coverage models, sign-off criteria and measurable quality goals for the owned verification scope. Identify technical … ensure that the DPU integrates successfully into complete systems. Required Skills and Experience: Strong knowledge of, and extensive hands-on coding experience with, SystemVerilog and UVM, including the architecture, implementation and review of complex verification environments. Hands-on verification experience in standard on-chip bus protocols such as AMBA ...