4 of 4 SystemVerilog Jobs in Peterborough

lead the entire ASIC development cycle, combining challenging design work with technical leadership. Candidates should have significant experience in digital design, particularly with SystemVerilog, and be comfortable mentoring others while improving design methodologies. A competitive salary and benefits package are included, providing opportunities for stock options and employee stock purchases. ...

Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi‐chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design teams test plans … Engineering or Computer Science 6+ years and current hands‐on experience in block‐level/IP‐level/SoC‐level verification Proficiency in Verilog, SystemVerilog Familiarity with industry‐standard EDA tools for simulation and debug Deep experience with UVM‐based testbenches Experience with modern programming languages like Python Knowledge ...

Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design teams test plans … Engineering or Computer Science 5+ years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based testbenches Experience with modern programming languages like Python Knowledge ...

concept through to full production maturity Support product definition activities through feasibility studies, architecture development, and FPGA-based digital emulation Develop RTL designs in SystemVerilog that meet system performance, functionality, and quality requirements Create comprehensive block-level verification environments and testbenches to validate digital functionality Perform digital synthesis and develop … digital design methodologies and best practices Demonstrate expertise in fully synthesised digital design flows, including RTL development and logic synthesis Be highly proficient in SystemVerilog and modern digital EDA toolchains Have experience applying timing and physical design constraints within automted place-and-route flows Understand production test requirements and have ...