6 of 6 SystemVerilog Jobs in Scotland

Qualifications Proven experience verifying complex SoC or subsystem-level designs. Strong background in DSP, wireless communication, or networking systems. Hands-on experience with Verilog, SystemVerilog, UVM, and/or VHDL. Solid understanding of verification methodologies, coverage, and debugging techniques. Experience with scripting languages such as Python, Tcl, Perl, or similar. ...

Engineering, Computer Engineering, Computer Science, or related field Deep understanding of hardware and digital design fundamentals Proven experience with large-scale SoC integration Strong SystemVerilog expertise Good understanding of UVM methodology Experience with complex RTL designs (e.g. high-speed I/O, CPUs, DSP, accelerators, NoCs) Ability to produce clear ...

/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience ...

Brand new, and cutting edge project, working for an exciting scale-up in the semiconductor space - to be based full-time from Scotland. Salary is circa £100k (PLUS AMAZING ADDITIONAL PACKAGE) I am looking for ...

delivering first-time success with complex mixed-signal ICs Metric-driven verification: planning, requirements extraction, directed & constrained-random verification, functional and code coverage analysis SystemVerilog, including SVA (SystemVerilog Assertions) Testbench design using verification frameworks such as UVM, OVM, e, or VMM Strong RTL/testbench debugging skills (including gate-level ...

more balanced and rewarding lifestyle. Key Responsibilities Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs Create and maintain testbenches using SystemVerilog and UVM Write and debug test cases to validate functionality, performance, and corner cases Perform block-level and full-chip verification, including simulation, coverage analysis … practices Manage and debug gate-level simulations Qualifications 10+ years of experience in digital and/or mixed-signal design verification Strong proficiency in SystemVerilog, UVM, and industry-standard simulation tools Solid understanding of digital design fundamentals, RTL design, and ASIC development flows Experience with scripting languages such as Python ...