11 of 11 SystemVerilog Jobs in Scotland

Electrical or Computer Engineering (or related discipline). Proven experience in digital IC design, ideally within AI accelerators, NPUs, GPUs, or high-performance ASICs. Strong RTL design skills using SystemVerilog/Verilog and familiarity with EDA tools for simulation, synthesis, and timing analysis. Knowledge of low-power design, high-speed interfaces (e.g., HBM, DDR5, PCIe), and standard on-chip protocols. More ❯

Electrical or Computer Engineering (or related discipline). Proven experience in digital IC design, ideally within AI accelerators, NPUs, GPUs, or high-performance ASICs. Strong RTL design skills using SystemVerilog/Verilog and familiarity with EDA tools for simulation, synthesis, and timing analysis. Knowledge of low-power design, high-speed interfaces (e.g., HBM, DDR5, PCIe), and standard on-chip protocols. More ❯

Electrical or Computer Engineering (or related discipline). Proven experience in digital IC design, ideally within AI accelerators, NPUs, GPUs, or high-performance ASICs. Strong RTL design skills using SystemVerilog/Verilog and familiarity with EDA tools for simulation, synthesis, and timing analysis. Knowledge of low-power design, high-speed interfaces (e.g., HBM, DDR5, PCIe), and standard on-chip protocols. More ❯

Electrical or Computer Engineering (or related discipline). Proven experience in digital IC design, ideally within AI accelerators, NPUs, GPUs, or high-performance ASICs. Strong RTL design skills using SystemVerilog/Verilog and familiarity with EDA tools for simulation, synthesis, and timing analysis. Knowledge of low-power design, high-speed interfaces (e.g., HBM, DDR5, PCIe), and standard on-chip protocols. More ❯

A leading Defence organisation are seeking multiple Firmware Engineers/FPGAEngineers on 12 month contracts (OutsideIR35) in Edinburgh tobe involved with FPGA firmware development across the Radar and Advanced Targeting line of business, working as part of a larger, multi More ❯

Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh More ❯

Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh More ❯

Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh More ❯

Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh More ❯

closure to achieve first-silicon success. Key Responsibilities Collaborate with design and architecture teams to define and implement verification strategies for AI accelerator blocks and SoC subsystems. Build scalable SystemVerilog/UVM testbenches, including test plans, monitors, checkers, scoreboards, and constrained-random stimulus. Perform coverage-driven and assertion-based verification, analyse coverage reports, and close functional and code coverage gaps. … incorporating high-level models and test generators. Qualifications Proven experience in digital IC design verification, preferably with exposure to CPU, GPU, NPU, or AI accelerator IP. Strong skills in SystemVerilog, UVM, and scripting languages such as Python, C++, Perl, or TCL. Solid understanding of computer architecture, memory hierarchies, and standard interconnects (e.g., AMBA/AXI, NoC). Familiarity with formal More ❯

Brand new, and cutting edge project, working for an exciting scale-up in the semiconductor space - to be based full-time from Scotland. Salary is circa £100k (PLUS AMAZING ADDITIONAL PACKAGE) I am looking for a SOC Chip design Lead More ❯