26 to 36 of 36 SystemVerilog Jobs in Scotland

scale-up environment. The role requires 10–20 years of full-chip delivery experience, expertise in Digital/AMS IP, verification with SystemVerilog, and hands-on responsibility across tape-out processes and PMIC power management. UK working rights are required. #J-18808-Ljbffr ...

synthesis and handoff, collaborating with architecture, verification, and physical design teams to solve complex silicon problems. The role targets senior engineers with expertise in SystemVerilog, RTL debugging, and timing closure, contributing to cutting-edge semiconductor solutions #J-18808-Ljbffr ...

About Analog DevicesAnalog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions ...

/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience ...

Edinburgh, ScotlandHardware & Software – Hardware/Full Time/HybridFor over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative ...

other verification engineers to deliver high-quality silicon solutions.ResponsibilitiesDevelop and execute comprehensive verification plans for complex mixed-signal ASIC designs.Create and maintain testbenches using SystemVerilog/UVM.Write and debug test cases to verify functionality, performance, and corner cases.Perform block-level and full-chip verification, including simulation, coverage analysis, and regression … degree in Electrical Engineering, Computer Engineering, or related field.10+ years of experience in digital and/or mixed-signal design verification.Strong proficiency in SystemVerilog, UVM, and simulation tools (Synopsys VCS, Cadence Xcelium).Solid understanding of digital design fundamentals, RTL design, and ASIC development flows.Experience with scripting languages (Python, Perl ...

engineers to deliver high-quality silicon solutions. ResponsibilitiesDevelop and execute comprehensive verification plans for complex mixed-signal ASIC designs. Create and maintain testbenches using SystemVerilog/UVM.Write and debug test cases to verify functionality, performance, and corner cases. Perform block-level and full-chip verification, including simulation, coverage analysis … degree in Electrical Engineering, Computer Engineering, or related field.10+ years of experience in digital and/or mixed-signal design verification. Strong proficiency in SystemVerilog, UVM, and simulation tools (Synopsys VCS, Cadence Xcelium).Solid understanding of digital design fundamentals, RTL design, and ASIC development flows. Experience with scripting languages (Python ...

design best practices.QualificationsEducation:BEng in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.Experience:• Deep knowledge of hardware and digital design fundamentals.• Strong SystemVerilog knowledge.• Experience with SoC integration.• Prior experience on complex RTL designs such as high‐speed I/O, CPUs, accelerators, or complex network‐on‐chip … architecture, verification, software, and system teams.• Ability to work effectively with internal and external stakeholders.• Ability to provide technical input during design reviews.Technology Stack:• SystemVerilog• Python scripting or programming• MATLABPhysical Requirements• Ability to work in a standard office environment and use a computer for extended periods.• Occasional travel ...

designs using advanced verification methodologies. Key responsibilities Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs Create and maintain UVM-based SystemVerilog testbenches Write, debug, and execute test cases to verify functionality, performance, and corner cases Perform block-level and full-chip verification, including simulation, coverage analysis … continuous improvement of design and verification best practices Qualifications 5+ years’ experience in digital and/or mixed-signal design verification Strong proficiency in SystemVerilog, UVM, and leading simulation tools (e.g., Synopsys VCS, Cadence Xcelium) Solid understanding of digital design principles, RTL design, and ASIC development flows Experience with scripting ...

development lifecycle. This is a hands-on verification role covering everything from planning and testbench development through to coverage closure and debugging. Responsibilities Develop SystemVerilog and UVM verification environments Create reusable verification components and testbenches Write assertions and functional coverage Debug complex RTL and simulation issues Drive verification activities from … sign-off Work closely with cross-functional engineering teams Help improve verification methodology and best practice About You You'll ideally have experience with: SystemVerilog UVM ASIC or SoC Verification Functional Coverage SystemVerilog Assertions (SVA) RTL Debug Verification Planning Experience within automotive or safety-critical semiconductor development would be beneficial ...

plus bonus and RSUs on top. The role Lead and mentor a small verification team Define and execute verification strategy (UVM/SystemVerilog) Oversee functional + formal verification Collaborate with design & architecture teams Drive coverage, quality, and delivery What you’ll bring Strong design verification background (digital or mixed-signal … Experience leading small teams or projects Skills in SystemVerilog, UVM, assertions, coverage Exposure to mixed-signal/ASIC environments (RNM a bonus) Why join Work on globally deployed technology Clear path into technical leadership Relocation support available High-impact role in a growing, innovative business Who this suits Senior Engineers ...