Oxfordshire, England, United Kingdom Hybrid / WFH Options
IC Resources
and UVM test benches Creation of UVM test benches System Verilog assertions Managing regression and debugging failures Scripting languages (e.g. Perl/Python/TCL) As this is a Senior role, team leadership skills will be welcomed and there could be an opportunity to take on more of a ‘lead more »
e, VMM Debugging skills - RTL - Testbench, OOP - Gate level (including SDF) Formal verification and verification qualification techniques Scripting experience with Ruby, sh/csh, TCL, Make, Perl - advantage This is a hybrid on-site position and will follow a 2+ day in-office work schedule, with in-office days based more »
Excellent knowledge of FPGA design verification and test bench simulation. Adept at working with version control systems. Good knowledge of scripting languages like Python, Tcl/Tk. Employee Benefits: We are offering two permanent position with a whole host of benefits including: 30 days holiday (in addition to 10.5 bank more »
