ASIC Design Engineer Jobs in the UK

101 to 102 of 102 ASIC Design Engineer Jobs in the UK

Application Specific Integrated Circuit Design Engineer

cambridge, east anglia, united kingdom
Canvendor
#Urgent_Opening_for Canvendor #Hiring : RTL Engineer (12+ Years Experience) | UK | Immediate Joiners Preferred Location: Cambridge, UK or Sophia, France Experience: 12+ Years Domain: Semiconductor/SoC/IP/Subsystem Verification Notice period: Immediate to 30days #Key_Requirements: Able to analyse/define/develop/write micro … Architechture specification for a sub-system Interact with Architect and understand the Module/Sub-system requirement Solid experience in SoC design/Integration aspects Need to be adept in finding design solution at SoC level Able to write glue logic/gasket/bridge modules as required … Experience in working large SoC/Chiplet design . Designs with Multi Clock/Reset/Voltage and Power domain Should be able to own and drive Quality check of the sub-system (CDC, RDC, Lint, DFT Lint) and take to closure Able to review and provide timing constraints More ❯
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Application Specific Integrated Circuit Design Engineer

Cambridge, south west england, united kingdom
Canvendor
#Urgent_Opening_for Canvendor #Hiring : RTL Engineer (12+ Years Experience) | UK | Immediate Joiners Preferred Location: Cambridge, UK or Sophia, France Experience: 12+ Years Domain: Semiconductor/SoC/IP/Subsystem Verification Notice period: Immediate to 30days #Key_Requirements: Able to analyse/define/develop/write micro … Architechture specification for a sub-system Interact with Architect and understand the Module/Sub-system requirement Solid experience in SoC design/Integration aspects Need to be adept in finding design solution at SoC level Able to write glue logic/gasket/bridge modules as required … Experience in working large SoC/Chiplet design . Designs with Multi Clock/Reset/Voltage and Power domain Should be able to own and drive Quality check of the sub-system (CDC, RDC, Lint, DFT Lint) and take to closure Able to review and provide timing constraints More ❯
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