15 of 15 Remote/Hybrid PCIe Jobs in the UK

DOORS . Design simulation using ModelSim or QuestaSim . FPGA development using vendor-specific tools (e.g., Xilinx or Intel toolchains). Knowledge of PCIe , Ethernet , Serial Communications , AXI4 or similar high-speed digital interfaces. Experience with object-oriented design , image-processing algorithms , or algorithm development using MATLAB . Familiarity with ...

experience Strong 'C' Programming Experience of mobile/satellite communications and their associated protocols Modulation techniques Network architectures Communication Protocols (e.g. SPI, UART, Ethernet, PCI-Express) Software Design methodologies (e.g. UML) System integration and performance analysis Full life cycle development in Agile/SCRUM working environment where quality and accuracy ...

research, and networking pipelines. What You'll Be Doing Designing and implementing latency-optimised FPGA systems in Verilog/SystemVerilog Developing high-speed modules (PCIe, Ethernet, DDR/QDR) with deep pipelining Using simulation and formal tools (Verilator, Cocotb, etc.) for validation Working across teams (ASIC, software, infra ...

Hard Real-Time embedded software development Experience of Real Time Operating Systems e.g FreeRTOS Desirable, but not essential: Communication Protocols (e.g. SPI, UART, Ethernet, PCI-Express) Experience in model-based development, using UML or using tools such as IBM's Rhapsody Strong problem solving at system and software component level ...

Hard Real-Time embedded software development Experience of Real Time Operating Systems e.g FreeRTOS Desirable, but not essential: Communication Protocols (e.g. SPI, UART, Ethernet, PCI-Express) Experience in model-based development, using UML or using tools such as IBM's Rhapsody Strong problem solving at system and software component level ...

ensure quality and performance targets are met. Skills, Experience, and Abilities Required: Expertise in System Verilog RTL design Hands-on experience with 100Gb Ethernet, PCIe Gen5, AMBA/AXI In-depth knowledge of FPGA/Adaptive SoC design flow, including place & route (P&R) and timing closure Proficiency in Vivado ...

software integration Familiarity with AMD Adaptive SoC development tools, including: AMD Vivado AMD Vitis High-Speed Networking Experience Hands-on experience with: 100Gb Ethernet PCIe (various generations) Understanding of high-throughput, low-latency networking architectures Development Workflow Competence Proficiency with Git , including branching strategies, code review, and CI/ ...

skills Formal Verification Desirable skills: Experience using SV UVM 1800.2 Familiarity with C/C++ Experience with any of the following storage interfaces: SAS, PCIe, NVMe (preferred) or SATA Salary and Package: Competitive Salaries Ranging From £50,000 – £130,000 (Depending on Level and experience) 10%-20% Bonus (based ...

generation FPGA and Adaptive SoC platforms and your experience looks highly relevant. They require someone with strong SystemVerilog RTL capability, confident across 100Gb Ethernet, PCIe Gen5 and AXI, and comfortable taking designs through to timing closure without fuss. Vivado and Vitis are central to the toolflow, and there's real ...

development, including kernel and device driver work Hands-on experience with Linux build processes , deployment, and testing Desirable/Nice-to-Have Knowledge of PCIe Experience with multi-core ARM processors Understanding of communication protocols Benefit package includes bonus, share options, 5% pension, healthcare, life assurance, illness protection, 32 days ...

Experience designing IP blocks (Nice to have) IP Block design for caches, coherency, memory subsystems, and interconnects Knowledge of RAS, QoS in fabrics, and PCIe/IO (a plus) Familiarity with Python Any experience with LLM accelerator chips, RISC-V processors, Cache and AMBA protocols will be advantageous. As well ...

building high-performance APIs that interface with hardware acceleration. Expect a mix of: Real-time C/C++ for wireless signal processing Linux, DPDK, PCIe, SIMD, modern C++ Hardware/software integration and performance tuning Designing, testing, optimising and owning your software through to delivery Working with DSP, FPGA, verification ...

Zephyr RTOS • Strong C and C++, plus Python and bash • Software flows for complex SoCs, co-simulation and hardware debug • Experience with 100GbE and PCIe • Proficient with Git and CI/CD • Familiarity with AMD Vivado and Vitis ...

integration, timing closure, place-and-route (P&R), constraints and optimisation . The role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA , and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows . Key Responsibilities Design high-performance … using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting timing, P&R and integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocks Drive timing closure using Vivado toolchains Develop automation using Python/Tcl scripting Collaborate with hardware, SoC, firmware and integration ...

RTOS . Youll contribute to board bring-up, hardware/software co-debug, system verification, driver-level development , and support high-speed interfaces including PCIe and 100GbE . Collaboration with global engineering teams is central to this role. Key Skills Required Embedded software development in C/C++ , plus scripting … Strong experience with bare-metal , Yocto Linux , Zephyr , RTOS SoC software flows , co-simulation, hardware debug and board bring-up High-speed interface experience: PCIe , Ethernet , 100GbE , SerDes Proficient with Git , CI/CD pipelines Advantageous: familiarity with AMD Adaptive SoC , Vivado , Vitis Whats on Offer Long-term programme with ...