1 to 25 of 30 Verification Engineer Jobs in the UK

Design Verification Engineer Edinburgh I have an exciting opportunity for a talented Verification Engineer to join an Edinburgh or Newbury based HW Team. As a Verification Engineer you will participate in all aspects of digital verification for complete mixed signal IC developments, work on complex verification systems and contribute towards improvements in … verification methodology within the business. This is a real chance for you to get heavily involved in cutting-edge projects working in a global organisation. Responsibilities: Definition of IC verification plan linking product requirements through to detailed testcases Leading teams of verification engineers to deliver thoroughly verified ICs Create reliable and reusable testbench for complex subsystems and … ICs Participate in verification specialist groups and contribute to the digital verification methodology discussions Supporting, and where necessary coaching, the verification team to follow, and improve, defined methodology practices Hands-on project design/verification involvement Required Skills and Qualifications BEng/BSc/MEng/MSc Degree or equivalent in Electronics/Computer Science or More ❯

Design Verification Engineer Edinburgh I have an exciting opportunity for a talented Verification Engineer to join an Edinburgh or Newbury based HW Team. As a Verification Engineer you will participate in all aspects of digital verification for complete mixed signal IC developments, work on complex verification systems and contribute towards improvements in … verification methodology within the business. This is a real chance for you to get heavily involved in cutting-edge projects working in a global organisation. Responsibilities: Definition of IC verification plan linking product requirements through to detailed testcases Leading teams of verification engineers to deliver thoroughly verified ICs Create reliable and reusable testbench for complex subsystems and … ICs Participate in verification specialist groups and contribute to the digital verification methodology discussions Supporting, and where necessary coaching, the verification team to follow, and improve, defined methodology practices Hands-on project design/verification involvement Required Skills and Qualifications BEng/BSc/MEng/MSc Degree or equivalent in Electronics/Computer Science or More ❯

Design Verification Engineer Edinburgh I have an exciting opportunity for a talented Verification Engineer to join an Edinburgh or Newbury based HW Team. As a Verification Engineer you will participate in all aspects of digital verification for complete mixed signal IC developments, work on complex verification systems and contribute towards improvements in … verification methodology within the business. This is a real chance for you to get heavily involved in cutting-edge projects working in a global organisation. Responsibilities: Definition of IC verification plan linking product requirements through to detailed testcases Leading teams of verification engineers to deliver thoroughly verified ICs Create reliable and reusable testbench for complex subsystems and … ICs Participate in verification specialist groups and contribute to the digital verification methodology discussions Supporting, and where necessary coaching, the verification team to follow, and improve, defined methodology practices Hands-on project design/verification involvement Required Skills and Qualifications BEng/BSc/MEng/MSc Degree or equivalent in Electronics/Computer Science or More ❯

Design Verification Engineer Edinburgh I have an exciting opportunity for a talented Verification Engineer to join an Edinburgh or Newbury based HW Team. As a Verification Engineer you will participate in all aspects of digital verification for complete mixed signal IC developments, work on complex verification systems and contribute towards improvements in … verification methodology within the business. This is a real chance for you to get heavily involved in cutting-edge projects working in a global organisation. Responsibilities: Definition of IC verification plan linking product requirements through to detailed testcases Leading teams of verification engineers to deliver thoroughly verified ICs Create reliable and reusable testbench for complex subsystems and … ICs Participate in verification specialist groups and contribute to the digital verification methodology discussions Supporting, and where necessary coaching, the verification team to follow, and improve, defined methodology practices Hands-on project design/verification involvement Required Skills and Qualifications BEng/BSc/MEng/MSc Degree or equivalent in Electronics/Computer Science or More ❯

Development Verification Engineer £55,000 - £65,000 + Training + Progression + 10% Bonus Bristol - Hybrid Are you a Development Verification Engineer or similar with expertise in SystemVerilog and UVM, seeking an autonomous role where your work directly contributes to the success of a leading semiconductor company, with opportunities for career growth, ongoing development, and the … strong global presence, they support clients in driving efficiency, safety, and sustainability across critical industries. In this role, you will develop and maintain SystemVerilog, UVM test benches, create new verification components, debug test cases, define functional coverage models, while supporting test bench architecture and design reviews using industry standard EDA tools. This is a full-time role, Monday to … Friday, 09:00AM - 17:00PM, with two days per week working from home. This role would suit a Development Verification Engineer with SystemVerilog and UVM skills, looking to join a world-leading semiconductor company with clear progression, specialist training, and the opportunity to boost earnings through a company bonus. The Role: Take the lead in creating and integrating More ❯

Junior Development Verification Engineer (Training and Progression) £30,000 - £35,000 + Training + Progression + 10% Bonus Bristol - Hybrid Are you an aspiring Verification Engineer looking to grow your expertise in SystemVerilog and UVM within a world-leading semiconductor company offering industry-leading training, structured progression, and the opportunity to increase your earnings through a … in the billions and a strong global presence, they support clients in driving efficiency, safety, and sustainability across critical industries. In this role, you'll work closely with experienced verification engineers to develop and maintain SystemVerilog - UVM test benches, assist in creating and integrating new verification components and debugging test cases. You'll receive hands-on training, tailored … development plans, and support to enhance your technical expertise, strengthen your understanding of EDA tools, and progress toward more senior verification roles as your experience grows. This is a full-time role, Monday to Friday, 09:00AM - 17:00PM, with two days per week working from home. This position would suit an aspiring Verification Engineer with foundational More ❯

Verification Engineer An excellent opportunity has arisen to join a global leader in advanced semiconductor technologies. This role offers the chance to work on cutting-edge 5nm designs, supporting the latest PCIe interfaces, protocols, and NAND flash solutions. While part of a large international organisation, the UK site operates with the feel of a fast-moving startup but … new requirements while minimising the risk of re-spins. The ASIC team is involved in every stage of the development flow—from requirements capture and architecture through to development, verification, tape-out, and post-silicon support. This provides excellent opportunities both for engineers looking to broaden their skills across the full lifecycle and for those who want to specialise … in areas such as UVM-based verification. As a Verification Engineer, you will join an industry-leading SoC development team tackling complex design challenges including high-speed interfaces, high-performance accelerators, and multi-CPU architectures. Team responsibilities span SoC architecture, RTL design, verification, synthesis, FPGA prototyping, and validation. Why Oxfordshire? Oxfordshire offers a fantastic quality of life More ❯

Verification Engineer An excellent opportunity has arisen to join a global leader in advanced semiconductor technologies. This role offers the chance to work on cutting-edge 5nm designs, supporting the latest PCIe interfaces, protocols, and NAND flash solutions. While part of a large international organisation, the UK site operates with the feel of a fast-moving startup but … new requirements while minimising the risk of re-spins. The ASIC team is involved in every stage of the development flow—from requirements capture and architecture through to development, verification, tape-out, and post-silicon support. This provides excellent opportunities both for engineers looking to broaden their skills across the full lifecycle and for those who want to specialise … in areas such as UVM-based verification. As a Verification Engineer, you will join an industry-leading SoC development team tackling complex design challenges including high-speed interfaces, high-performance accelerators, and multi-CPU architectures. Team responsibilities span SoC architecture, RTL design, verification, synthesis, FPGA prototyping, and validation. Why Oxfordshire? Oxfordshire offers a fantastic quality of life More ❯

Design Verification Engineer Manchester/Sheffield/Leeds UK REMOTE can be considered This is a fantastic opportunity to join a start-up who are just over 2 years old, as they make technological breakthroughs in security with a product line built on CHERI technology and RISC‐V cores. They have strong funding behind them and a leadership … renown companies and start-ups. With huge growth plans across the Silicon Design team this is a fantastic time to join the business! I am looking for a talented Verification Engineer to join a rapidly growing stealth mode start-up. The successful candidate will play a key role in the verification of hardware, specifically focusing on security … features utilizing CHERI technology. Responsibilities Collaborates with the design team to understand and define verification requirements for security features Develops and maintains verification plans, testbenches, and test scenarios using UVM methodology Executes test plans and verifies the correctness of hardware security features Works closely with the cross-functional teams to ensure the implementation meets design specifications and security More ❯

DV Engineer Quantum StartUp I am seeking a Senior Verification Engineer to join a rapidly growing HW Team in Cambridge. You will get the opportunity to work on cutting edge technology and in the area of quantum computing. No prior experience in quantum computing? No problem. You'll learn as you go while working alongside world-class … engineers in a truly cross-disciplinary environment. About the role As a Senior Verification Engineer , you’ll take full ownership of functional verification across their hardware systems. You’ll collaborate with a talented team of hardware designers and embedded software engineers to deliver trusted, high-performance solutions—verified from the ground up. With full visibility of the … stack, you’ll define verification strategies, implement robust test environments, and ensure confidence in every design you deliver. What you’ll do Work closely with hardware designers and system architects to define and own verification plans based on design specifications Develop scalable SystemVerilog testbenches , including checkers, coverage groups, and reference models Design and run self-checking, directed, and More ❯

DV Engineer Quantum StartUp I am seeking a Senior Verification Engineer to join a rapidly growing HW Team in Cambridge. You will get the opportunity to work on cutting edge technology and in the area of quantum computing. No prior experience in quantum computing? No problem. You'll learn as you go while working alongside world-class … engineers in a truly cross-disciplinary environment. About the role As a Senior Verification Engineer , you’ll take full ownership of functional verification across their hardware systems. You’ll collaborate with a talented team of hardware designers and embedded software engineers to deliver trusted, high-performance solutions—verified from the ground up. With full visibility of the … stack, you’ll define verification strategies, implement robust test environments, and ensure confidence in every design you deliver. What you’ll do Work closely with hardware designers and system architects to define and own verification plans based on design specifications Develop scalable SystemVerilog testbenches , including checkers, coverage groups, and reference models Design and run self-checking, directed, and More ❯

DV Engineer Quantum StartUp I am seeking a Senior Verification Engineer to join a rapidly growing HW Team in Cambridge. You will get the opportunity to work on cutting edge technology and in the area of quantum computing. No prior experience in quantum computing? No problem. You'll learn as you go while working alongside world-class … engineers in a truly cross-disciplinary environment. About the role As a Senior Verification Engineer , you’ll take full ownership of functional verification across their hardware systems. You’ll collaborate with a talented team of hardware designers and embedded software engineers to deliver trusted, high-performance solutions—verified from the ground up. With full visibility of the … stack, you’ll define verification strategies, implement robust test environments, and ensure confidence in every design you deliver. What you’ll do Work closely with hardware designers and system architects to define and own verification plans based on design specifications Develop scalable SystemVerilog testbenches , including checkers, coverage groups, and reference models Design and run self-checking, directed, and More ❯

An exciting opportunity has arisen for a Validation & Verification Engineer to join a leading flight software team working on cutting-edge space missions. This role offers the chance to contribute to next-generation orbital debris removal and satellite servicing projects, a truly unique opportunity to make an impact on the future of space sustainability. We’re looking for … s ready to take the next step in their career and play a key role in ensuring flight software reliability, performance, and safety. You’ll be responsible for the verification and validation (V&V) of onboard flight software for satellite missions, defining solutions based on system requirements and collaborating across subsystems to ensure robust, high-quality software delivery. Key … Responsibilities: Participate in the validation and verification of flight software for satellite onboard computers. Review technical specifications and requirements documents (SRS, ICD, SDD, etc.). Design, implement, and automate test cases and scripts. Develop and maintain test environments and simulators. Identify and implement test equipment solutions. Collaborate with subsystem teams to define software needs and interfaces. Contribute to technical More ❯

An exciting opportunity has arisen for a Validation & Verification Engineer to join a leading flight software team working on cutting-edge space missions. This role offers the chance to contribute to next-generation orbital debris removal and satellite servicing projects, a truly unique opportunity to make an impact on the future of space sustainability. We’re looking for … s ready to take the next step in their career and play a key role in ensuring flight software reliability, performance, and safety. You’ll be responsible for the verification and validation (V&V) of onboard flight software for satellite missions, defining solutions based on system requirements and collaborating across subsystems to ensure robust, high-quality software delivery. Key … Responsibilities: Participate in the validation and verification of flight software for satellite onboard computers. Review technical specifications and requirements documents (SRS, ICD, SDD, etc.). Design, implement, and automate test cases and scripts. Develop and maintain test environments and simulators. Identify and implement test equipment solutions. Collaborate with subsystem teams to define software needs and interfaces. Contribute to technical More ❯

Position Overview As a Senior Design Verification Engineer , you will apply industrial-strength verification to both system and block-level designs, including RISC-V cores, OTBN (cryptographic CPU), AES accelerators, and peripherals like USB, I2C, and SPI. Key Responsibilities Design, implement, and debug block/system-level tests and testbenches using SystemVerilog and UVM Develop test and … new and updated designs Triage and debug nightly regressions Review contributions to open-source projects Enhance test and CI infrastructure Collaborate on academic/industry publications Stay current with verification best practices and introduce improvements Candidate Requirements Essential: 5+ years industry experience in design verification Strong SystemVerilog and UVM expertise Experience across the full verification cycle (planning … equivalent Desirable: Experience with multiple hardware block types Knowledge of security countermeasures (fault injection, side-channel attacks) Experience with RISC-V ISA or other instruction sets Familiarity with formal verification tools (e.g., JasperGold) Benefits 25 days annual leave + 8 bank holidays Employer pension contribution Private medical insurance, income protection, critical illness and life cover Opportunities to attend industry More ❯

client is a globally recognised semiconductor company developing a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic … shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA More ❯

client is a globally recognised semiconductor company developing a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic … shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA More ❯

client is a globally recognised semiconductor company developing a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic … shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA More ❯

client is a globally recognised semiconductor company developing a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic … shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA More ❯

work powering real-world products used by world-leading brands across gaming, wireless PC peripherals, sports and fitness, mobile accessories, consumer electronics, healthcare, and automation . As an ASIC Verification Engineer , you’ll focus on the verification of WiFi SoCs , with a strong emphasis on low-power design . You’ll develop advanced UVM-based testbenches, collaborate … with cross-functional teams, and help drive verification strategies for next-generation ultra-low-power wireless devices. Responsibilities Develop and implement UVM-based testbenches for ASIC verification Verify low-power features and optimise for energy efficiency Contribute to the verification of complex SoC designs Debug and analyse hardware design issues Collaborate with design and architecture teams to … ensure verification quality Qualifications Bachelor’s or Master’s in Electrical Engineering (or related field) Strong experience in ASIC verification and digital hardware design Skilled in SystemVerilog/UVM testbench development Knowledge of low-power verification techniques Familiarity with C for testbench development is a plus Experience in WiFi/wireless SoC development is desirable Excellent communication More ❯

Design Verification Engineers — Next-Generation AI ASICs Cambridge or Edinburgh An innovative fabless semiconductor start-up is developing cutting-edge AI accelerator chips designed to deliver an order-of-magnitude performance improvement while dramatically reducing power consumption. I am seeking experienced Verification Engineers to ensure the functional correctness and robustness of complex AI accelerator designs. You will play … a key role in developing advanced verification environments and driving coverage closure to achieve first-silicon success. Key Responsibilities Collaborate with design and architecture teams to define and implement verification strategies for AI accelerator blocks and SoC subsystems. Build scalable SystemVerilog/UVM testbenches, including test plans, monitors, checkers, scoreboards, and constrained-random stimulus. Perform coverage-driven and … assertion-based verification, analyse coverage reports, and close functional and code coverage gaps. Debug complex hardware–software interactions, reproduce silicon issues in simulation, and work closely with RTL, architecture, and software engineers to resolve them. Develop verification frameworks that scale across unit-level simulation, emulation, and post-silicon validation, incorporating high-level models and test generators. Qualifications Proven More ❯

Job Title: Senior Hardware Verification Engineer Location: England, United Kingdom (Remote anywhere inside the country) About the Role: We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity … etc. Qualifications: BS/MS in Electrical Engineering, Computer Engineering or Computer Science 8+ years and current hands-on experience in block-level/IP-level/SOC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based testbenches Experience with modern programming languages like Python Knowledge of … AXI, APB, and AHB Understanding of ARM CHI protocol is a plus Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NOCs Experience with formal verification techniques, emulation platforms is a plus Excellent problem-solving skills and attention to detail Strong communication and collaboration skills rich.goldstein@bayasytems.com More ❯

and collaboration, they are working on missions that aim to capture and retire multiple satellites, contributing to a cleaner and safer space environment. Your new role As a Validation & Verification Engineer, you'll join a busy flight software team responsible for ensuring the reliability and performance of embedded real-time software used in orbital debris missions. You'll … implementing automated test scripts Proficient in Python, including dependency management and virtual environments Experience with software validation facilities (numerical, hybrid, or hardware) Familiarity with Git Experience in validation and verification of software for the space industry Experience with real-time embedded systems (C/C++) Understanding of communication protocols such as PUS, CCSDS, CAN, SpaceWire Solid grasp of the More ❯

and collaboration, they are working on missions that aim to capture and retire multiple satellites, contributing to a cleaner and safer space environment. Your new role As a Validation & Verification Engineer, you'll join a busy flight software team responsible for ensuring the reliability and performance of embedded real-time software used in orbital debris missions. You'll … implementing automated test scripts Proficient in Python, including dependency management and virtual environments Experience with software validation facilities (numerical, hybrid, or hardware) Familiarity with Git Experience in validation and verification of software for the space industry Experience with real-time embedded systems (C/C++) Understanding of communication protocols such as PUS, CCSDS, CAN, SpaceWire Solid grasp of the More ❯

and collaboration, they are working on missions that aim to capture and retire multiple satellites, contributing to a cleaner and safer space environment. Your new role As a Validation & Verification Engineer, you'll join a busy flight software team responsible for ensuring the reliability and performance of embedded real-time software used in orbital debris missions. You'll … implementing automated test scripts Proficient in Python, including dependency management and virtual environments Experience with software validation facilities (numerical, hybrid, or hardware) Familiarity with Git Experience in validation and verification of software for the space industry Experience with real-time embedded systems (C/C++) Understanding of communication protocols such as PUS, CCSDS, CAN, SpaceWire Solid grasp of the More ❯