26 to 50 of 71 Verilog Jobs in the UK excluding London

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

writing tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

firmware, and software. Collaborate with multidisciplinary teams to deliver next-generation quantum technologies. What Were Looking For: Strong experience in FPGA programming (VHDL/Verilog/SystemVerilog) and DSP implementation. Knowledge of digital and RF hardware, with hands-on experience in embedded systems. Experience with standard hardware interfaces ...

Engineer role in Southampton: Degree in Electrical Engineering, Computer Science, or similar 5+ years’ experience as an FPGA Engineer Strong VHDL and/or Verilog development experience Knowledge of FPGA toolchains (Vivado, Quartus, ModelSim) Experience with SoC devices (e.g. Zynq UltraScale+) Desirable: Video/RF protocols (MIPI, SDI) Python ...

technical design decisions Ensure robust, scalable and reusable OpenCPI-based implementations Develop OpenCPI workers and containers in C/C++ and HDL (VHDL/Verilog where required) Integrate DSP chains into FPGA and embedded Linux environments Conduct trade-off analysis across performance, latency and resource utilisation Support hardware/software ...