51 to 70 of 70 Perl Jobs

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Knowledge of low-power micro-architecture techniques Understanding of high-performance CPU micro-architecture strategies and trade-offs Experience with scripting languages such as Perl or Python Compensation & benefits You can expect a competitive base salary, RSUs, and bonus. Visa sponsorship is available for engineers already based in the UK. ...

like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh, TCL, Make, Perl Power aware verification (using CPF/UPF) This position is based in Edinburgh. This is a hybrid remote position and will follow a 2+ ...

power microarchitecture techniques. Understanding of high performance techniques and trade-offs in a CPU microarchitecture. Experience using a scripting language such as Perl or Python. If this role is of any interest please apply directly on LinkedIn or send a copy of your CV to nh@eu-recruit.com. By applying ...

OpenText expertise, including Document Access, Enterprise Scan, Document Pipeline tuning, and high availability/DR setup for Archive Center. Experience with automation and scripting (Perl, Shell) and ABAP exits/BADIs for monitoring and automation. Exposure to DVM tooling and third party solutions (e.g., PBS, TJC) for analytics, purge/ ...

/IP and other common network protocols. You are proficient with at least one high-level scripting language (such as Python, Ruby, or Perl). You should have a bias toward automation and track record of creating automated solutions. You have experience operating distributed systems and diagnosing and resolving complex … Experience in site reliability engineering (SRE), systems engineering, systems administration, DevOps, security administration, or network administration - Experience in any of the following: Python, Java, Perl, PHP, Ruby, Bash, Shell or equivalent - Experience working with Linux PREFERRED QUALIFICATIONS - Experience maintaining the resilience and reliability of services by troubleshooting deployment failures, creating ...

Server (SLES) environments. • Monitor systems, troubleshoot issues, and optimise performance. • Ensure system security and compliance with industry standards. • Automate tasks using Bash, Python, or Perl scripts. • Design, deploy, and manage Linux workloads in Azure. • Implement and manage virtual networks, storage, and Azure resources. • Ensure high availability and disaster recovery … Hands-on SAP HANA administration and optimisation experience. • Proficiency with Microsoft Azure, including ARM templates, Azure CLI, and PowerShell. • Strong scripting skills (Bash, Python, Perl) for automation. • Experience supporting large-scale enterprise environments. • Excellent problem-solving and collaboration skills. • SUSE or Microsoft Azure certifications are a plus. Apply today ...

logic design principles and their implications on timing and power. Understanding of register renaming, instruction scheduling, and speculative execution. Experience using Python or Perl for design automation and analysis. Keywords: CPU Design/RTL Engineer/Verilog/VHDL/Micro-architecture/Out-of-Order Execution/Low Power … Design/PPA/Instruction Fetch/Logic Design/Python/Perl/Cambridge/Semiconductor If you are interested in this RTL Design Engineer position, please send a CV to ts@eu-recruit.com By applying to this role you understand that we may collect your personal data ...

RTL Design Engineer - CPU/Semiconductor/Microprocessor Architecture/Verilog/VHDL We're partnered with a global Semicon company, and they need a CPU RTL Design Engineer to work on next generation high ...