126 to 150 of 191 Remote SystemVerilog Jobs

The company offers a dynamic work environment, excellent benefits, and opportunities for innovation. As a Senior Digital FPGA Engineer, you will develop FPGAs using SystemVerilog, collaborating closely with software and machine learning teams to build low-latency, high-throughput applications. Required Skills and Experience: FPGA design, development, and testing experience … Proficiency in SystemVerilog, VHDL, and/or Verilog Skills in C/C++ or Python Experience with Quartus and/or Vivado tools Knowledge of low latency, machine learning, or neural network architectures is a plus but not essential If interested in this hybrid Senior Digital FPGA Engineer role in More ❯

offers a dynamic work environment, excellent benefits, and opportunities for innovation and growth. As a Senior Digital FPGA Engineer, you will develop FPGAs using SystemVerilog, collaborating closely with software and machine learning teams to build low-latency, high-throughput applications. Required skills and experience: Experience in FPGA design, development, and … testing Proficiency in SystemVerilog, VHDL, and/or Verilog Programming skills in C/C++ or Python Experience with Quartus and/or Vivado tools Knowledge of low latency, machine learning, or neural network architectures is a plus but not essential If this hybrid Senior Digital FPGA Engineer position in More ❯

Cyber Security innovator. What You'll Do: Design and verify RTL for FPGAs (Xilinx Zynq SoC, Kintex Ultrascale) Build simulation & test environments (Verilog/SystemVerilog) Perform functional & post-P&R simulations Automate and execute test cases based on system requirements Debug hardware issues using Chipscope, scopes, etc. Report defects, track … issues, and support development teams Must-Have Skills: 10+ years in FPGA design/validation Strong Verilog/SystemVerilog experience Proficiency with Xilinx Vivado Ethernet protocol implementation in FPGA Simulation tools (ModelSim, ISIM) Familiarity with C programming Hardware debug tools Nice to Have Skills and Experience: L2/L3 switching More ❯

Join to apply for the Design Engineer (AI/ML) role at Arm 1 week ago Be among the first 25 applicants Join to apply for the Design Engineer (AI/ML) role at Arm Job Description Are you passionate More ❯

1 day ago Be among the first 25 applicants Get AI-powered advice on this job and more exclusive features. Job ID 2024-13226 Date posted 13/01/2025 Location Manchester, United Kingdom Category Architecture Job Overview In More ❯

About Us Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop new and highly innovative electronic products faster and more cost-effectively. Our customers use our tools More ❯

Firmware/FPGA Engineers - All levels (All UK Sites) Leonardo Basildon, England, United Kingdom Join or sign in to find your next job Join to apply for the Firmware/FPGA Engineers - All levels (All UK Sites) role at Leonardo More ❯

About Us Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop new and highly innovative electronic products faster and more cost-effectively. Our customers use our tools More ❯

About Us Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop new and highly innovative electronic products faster and more cost-effectively. Our customers use our tools More ❯

success with complex mixed signal IC's. Metric driven verification - verification planning, requirements extraction - Directed and constrained random verification - Functional and code coverage analysis SystemVerilog - SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills - RTL - Testbench, OOP - Gate level (including SDF) Strong ability More ❯

success with complex mixed signal IC’s. Metric driven verification - verification planning, requirements extraction - Directed and constrained random verification - Functional and code coverage analysis SystemVerilog - SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills - RTL - Testbench, OOP - Gate level (including SDF) Strong ability More ❯

and milestones clearly and consistently Support synthesis and physical design teams during integration and bring-up phases Verification Responsibilities Develop and maintain UVM/SystemVerilog testbenches for functional verification Write both directed and random tests to verify design correctness and improve coverage Run regressions and assist with debugging RTL and … behavior Work closely with architects and RTL designers in an iterative development cycle Design Requirements 0–2 years of experience in RTL design using SystemVerilog or VHDL Solid foundation in digital logic design and computer architecture Exposure to or strong interest in GPU, AI accelerators, or vector processors Familiarity with … Engineering, or a related discipline Verification Requirements 0–2 years of hands-on experience with hardware verification (academic or internship projects count) Familiar with SystemVerilog and basic UVM concepts Interest or exposure to functional coverage, assertions, and constrained-random testing Understanding of GPU/AI workloads or RISC-V architecture More ❯

formal verification. Staff Engineers are also encouraged to mentor junior members Required Skills and Experience : Tried understanding of digital hardware design and Verilog/Systemverilog HDL Experienced in one or more of various verification methodologies - UVM/OVM, formal, power aware verification, emulation Exposure to all stages of verification: requirements … collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Experience with relevant coding languages: SystemVerilog, C++ and python Good Problem Solving and Debugging skills. "Nice To Have" Skills and Experience : Experience with ARM Architecture Knowledge of cache coherency protocol and AMBA protocols like More ❯

coverage-driven methodology) Estimate cost and schedule Develop and debug an advanced UVM-based verification environment Develop coverage strategy and tests for parameterized IPs (SystemVerilog) Perform functional, performance, and power verification Identify blocks lacking robustness against faults and propose optimal safety mechanisms Provide support to the design team throughout project … to develop both directed and constrained-random stimulus to ensure robust test scenarios. You have hands-on experience in RTL coding , using Verilog or SystemVerilog, and are capable of running and interpreting lint checks , as well as performing CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) analyses to ensure More ❯

Firmware/FPGA Engineer Location: Multiple locations across the UK (Bristol, Bedfordshire, London, Essex) Contract Type: Inside IR35 Clearance: British Sole Passport Holder and SC Cleared or SC Clearable. Who: A leading services company specializing in Defence systems dedicated to More ❯

Social network you want to login/join with: col-narrow-left Client: People Source Consulting trading as Experis Location: luton, bedfordshire, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 4 Posted: 12.05.2025 More ❯

Social network you want to login/join with: People Source Consulting trading as Experis Location: bedford, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 6 Posted: 07.06.2025 Expiry Date: 22.07.2025 col-wide More ❯

Social network you want to login/join with: Firmware/FPGA Engineer, watford, hertfordshire col-narrow-left Client: People Source Consulting trading as Experis Location: watford, hertfordshire, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow More ❯

Job Title: Firmware/FPGA Engineer Location: Multiple locations across the UK (Bristol, London, Essex) Contract Type: Inside IR35 About Us: We are a leading services company specializing in Defence systems. Our team is dedicated to designing, developing, and delivering More ❯

Job Description As a Digital Design Engineer, you will be responsible for the digital design and RTL coding using Verilog or System Verilog. Integrating modules at SoC and work hands-on in the development cycle, especially in frontend domain until More ❯

Firmware/FPGA Engineer Location: Multiple locations across the UK (Bristol, Bedfordshire, London, Essex) Contract Type: Inside IR35 Clearance: British Sole Passport Holder and SC Cleared or SC Clearable. Who: A leading services company specializing in Defence systems dedicated to More ❯

Firmware/FPGA Engineer Location: Multiple locations across the UK (Bristol, Bedfordshire, London, Essex) Contract Type: Inside IR35 Clearance: British Sole Passport Holder and SC Cleared or SC Clearable. Who: A leading services company specializing in Defence systems dedicated to More ❯

Firmware/FPGA Engineer Location: Multiple locations across the UK (Bristol, Bedfordshire, London, Essex) Contract Type: Inside IR35 Clearance: British Sole Passport Holder and SC Cleared or SC Clearable. Who: A leading services company specializing in Defence systems dedicated to More ❯

/Computer Science or other related discipline. Metric driven verification - verification planning, requirements extraction - Directed and constrained random verification - Functional and code coverage analysis SystemVerilog - SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills - RTL - Testbench, OOP - Gate level (including SDF) Scripting experience More ❯

top level and running block & top-level simulations. Participate in all aspects of Mixed-signal design flow - Micro-architecture, Design partitioning, RTL Verilog/SystemVerilog Design, Generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC, RDC, UPF. Working closely with P&R team to generate a … Working with analog and digital verification engineers to come up with complex test scenarios for pre-silicon verification. Supporting analog team to develop AMS, SystemVerilog or Verilog-real behavioral models. Developing detailed block & chip level design documents and collateral. Holding and participating in key design reviews and completion of various … handheld, data conversion, and power management. Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or related discipline. Fluent in Verilog/SystemVerilog RTL for digital CMOS circuit design. Strong understanding of ASIC design methodology. Strong understanding of Linting, CDC & RDC tools. Strong understanding of block-level & chip More ❯