Senior FPGA Verification Engineer
- Location
- Oxford, England, United Kingdom
develop critical simulation infrastructure, contributing directly to the success of the FPGA team. Key responsibilities include: Architect, develop, and maintain advanced UVM/SystemVerilog verification environments for complex FPGA designs. Define and execute comprehensive verification plans, including constrained-random testing, functional coverage, and code coverage analysis. Collaborate with RTL design … robust verification strategies, and work collaboratively across design teams to ensure high-quality outcomes. You’d be a great fit with: Strong proficiency in SystemVerilog and UVM for architecting advanced verification environments. Experience using Python for test automation and scripting. Demonstrated ability to lead requirements gathering and define verification plans ...