126 to 150 of 181 Verilog Jobs

School Diploma or equivalent and 6 years relevant experience. Have an active DoD Top Secret/SCI with full scope polygraph at the time of consideration. Have experience with Verilog, System Verilog, or VHDL. Have experience with industry-standard EDA tools and processes (synthesis, P&R, simulation, etc.)? Have the ability to learn new skills quickly Preferred Requirements • Have experience More ❯

the most innovative imaging systems in development today. Key Responsibilities Define digital architecture and block-level concepts Develop detailed specifications for digital functions RTL design and verification using SystemVerilog, Verilog, or VHDL Collaborate closely with analog IC designers and subcontractors Debug RTL and gate-level simulation failures Write scripts in Python, Perl, or similar for automation and testing Qualifications Degree More ❯

AI/ML. The work will include building strategy, verification plans, testbenches and sign-off using the Axiomise six-dimensional coverage methodology. You are expected to be confident in Verilog/VHDL as well as fluent in SVA and Tcl/Perl/Python and Unix/Linux scripting. For additional details and the most recent updates, hit "Apply for More ❯

AI/ML. The work will include building strategy, verification plans, testbenches and sign-off using the Axiomise six-dimensional coverage methodology. You are expected to be confident in Verilog/VHDL as well as fluent in SVA and Tcl/Perl/Python and Unix/Linux scripting. For additional details and the most recent updates, hit "Apply for More ❯

in ASIC and SoC design. We are looking for engineers with proven experience in several of the following areas: •Computer architectures (ARM or RISC-V) •FPGA Development •VHDL/Verilog •SystemVerilog •UVM Verification •Interconnect protocols such as AXI or OCP Requirements: •Be part of innovative, high-impact projects in a fast-moving industry •Collaborate with a global team of expert More ❯

senior group will deliver high-speed compute infrastructure integrated directly into trading, research, and networking pipelines. What You’ll Be Doing Designing and implementing latency-optimised FPGA systems in Verilog/SystemVerilog Developing high-speed modules (PCIe, Ethernet, DDR/QDR) with deep pipelining Using simulation and formal tools (Verilator, Cocotb, etc.) for validation Working across teams (ASIC, software, infra More ❯

senior group will deliver high-speed compute infrastructure integrated directly into trading, research, and networking pipelines. What You’ll Be Doing Designing and implementing latency-optimised FPGA systems in Verilog/SystemVerilog Developing high-speed modules (PCIe, Ethernet, DDR/QDR) with deep pipelining Using simulation and formal tools (Verilator, Cocotb, etc.) for validation Working across teams (ASIC, software, infra More ❯

Essential Skills & Experience: Knowledge/Experience of developing/modelling/simulating software in at least one of the following areas: RF telecommunications, waveforms, OSI model, SIGINT, EW VHDL VERILOG Experience with SDR architecture Agile development methodologies. C#, C, C++, Python and Database architecture. Desirable Experience XML Networked systems JICD Restful and/or RPC API Library agnostic code development More ❯

Essential Skills & Experience: Knowledge/Experience of developing/modelling/simulating software in at least one of the following areas: RF telecommunications, waveforms, OSI model, SIGINT, EW VHDL VERILOG Experience with SDR architecture Agile development methodologies. C#, C, C++, Python and Database architecture. Desirable Experience XML Networked systems JICD Restful and/or RPC API Library agnostic code development More ❯

growth of team members through regular mentoring, coaching, and feedback Skills, Knowledge & Expertise: Track record of building and leading high performing collaborative teams. Expert knowledge of an RTL design (Verilog, SystemVerilog) for complex ASIC/FPGA products. A strong skillset in delivery of digital designs for ASIC and FPGA. Optimisation of timing and hardware resources for high throughput data or More ❯

PhD (or equivalent experience) in Computer Science, Computer Engineering, or related fields Experience with application development in Python Knowledge of open-source development practices and community engagement Familiarity with Verilog/SystemVerilog and EDA tool flows, especially for design verification Strong teamwork and communication skills Preferred Qualifications (not required): Experience working with a silicon development team Knowledge of SoC architecture More ❯

working with the PCB layout team to optimize placement, signal integrity, fitment, etc. Strong documentation and communication skills Experience with firmware or microcontrollers a plus Experience with VHDL/Verilog a plus Workplace Options: This position is Hybrid/Flex. While on-site, you will be a part of the Manassas, VA location. Equal opportunity employer as to all protected More ❯

in all phases of PCB design including component selection, SPICE and power analysis, schematic entry, and collaboration with layout teams. Experience with OrCAD Capture, microcontrollers, and optionally VHDL/Verilog or firmware development. Moseley Technical Services, Inc. is an AA/EEO/Veterans/Disabled Employer. Still have questions? Reach out to Jarrett at What to Expect Applicants selected More ❯

ll be in your hands. As an engineer we know you'll want to know about our tech stack - and the experience you'll need there - it includes: FPGA, Verilog, C/C++, RF engineering. If you think you got what it takes to drive the development of our control systems, enable the seamless integration of classical and quantum computing More ❯

Engineering, Computer Engineering, or Computer Science. Solid understanding of emulation methodologies and flows. Experience with emulation platforms such as ZeBu, Palladium, or Strato. Familiarity with RTL languages (SystemVerilog/Verilog) and UVM-based verification environments. Hands-on experience in compiling and debugging large-scale designs on emulation platforms. Proficiency in scripting (Python, Perl, or similar) to automate workflows and diagnostics. More ❯

Be responsible for defining, estimating and tracking of own work YOU SHOULD HAVE: Over 2 years recent and relevant module design experience within at least one HDL (VHDL/Verilog/SystemVerilog) Knowledge of computer systems and architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning tools (Git, SVN More ❯

tapeout on next-generation chip architectures in areas like memory, interconnect, and high-speed interface design. Key Responsibilities: + Develop and Integrate designs of RTL for digital blocks (using Verilog/SystemVerilog/VHDL) + Undertake Digital IC Design processes & Perform design synthesis, linting + Complete projects from conception to completion Skills Required: + Experience with frontend RTL Design + … Strong Experience with SystemVerilog, Verilog or VHDL + Has had exposure to ASIC design flow (Lint, syntheisis, simulation) + Digital Design Principles experience pipelining, clock domain crossing Further Details: This role offers remote working with a potential visit into the office every month. A competitive salary, bonus scheme, and a strong benefits package. If you are a driven and experienced More ❯

a great opportunity to work on advanced radar and sensor technologies that make a real difference in security applications worldwide. You’ll need: FPGA Design experience in VHDL or Verilog Strong competency with Xilinx Vivado A background in DSP would be desirable More ❯

role involves working on FPGA-based systems with a focus on throughput, reliability, and integration within a larger hardware-software environment. Key Skills: Solid FPGA development experience VHDL or Verilog (SystemVerilog a plus) Knowledge of high-speed interfaces (e.g., PCIe, DDR, Ethernet) To Apply: Submit your CV below.. More ❯

future of AI, HPC, and other advanced technologies. Required Skills & Experience Master's degree in a relevant field. Proven experience in 3 successful tapeouts Expertise in UVM/System Verilog Experience with Formal Verification Experience with scripting languages such as Python, Perl or Bash Knowledge of NoC, PCIe, DDR and other standard peripherals is desirable but not essential This Senior More ❯

block level definition & specification ADDITIONAL USEFUL EXPERIENCE: System simulation Integrated single chip RF + digital baseband projects Top level chip simulation and functional verification Analogue behavioral language modeling (e.g. Verilog-AMS) Mixed-mode simulation environments (e.g. mixed Verilog and device level) Direct conversion Rx and Tx architectures and associated considerations DFT and BIST for analogue and RF circuits Silicon test More ❯

help build low-latency/high-throughput applications. What skills and experience is required: FPGA Design, development and testing experience Previous experience in using SystemVerilog, VHDL and/or Verilog Exposure to Quartus and/or Vivado Any exposure or understanding of low latency, machine learning, or neutral network architectures would be beneficial but not essential. *Visa Sponsorship is available More ❯

years of experience in frontend RTL design. Solid understanding of digital design principles, including pipelining, clock domain crossing, and low-power design techniques, high performance design techs. Proficient in Verilog/SystemVerilog/VHDL. Familiar with ASIC design flow and tools. Experience with GPU design or computer graphics architecture. Familiarity with high-speed interfaces and memory subsystems. Familiarity with modern More ❯

years of experience in frontend RTL design. Solid understanding of digital design principles, including pipelining, clock domain crossing, and low-power design techniques, high performance design techs. Proficient in Verilog/SystemVerilog/VHDL. Familiar with ASIC design flow and tools. Experience with GPU design or computer graphics architecture. Familiarity with high-speed interfaces and memory subsystems. Familiarity with modern More ❯

and CAN. Good understanding of how satellite systems work together. Experience writing test plans and running verification on avionics. Nice to have (but not essential): FPGA development (VHDL or Verilog). Python scripting for test automation. Experience working in a cleanroom or handling flight hardware. Background in GNSS, time sync, or radiation tolerance in LEO. Why this role? Flexible hybrid More ❯