Luton, Bedfordshire. The Firmware Engineer will deliver Firmware for complex digital systems that meet challenging future customer requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Auto-generated code using model More ❯
Luton, Bedfordshire. The Firmware Engineer will deliver Firmware for complex digital systems that meet challenging future customer requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Auto-generated code using model More ❯
Luton, Bedfordshire. The Firmware Engineer will deliver Firmware for complex digital systems that meet challenging future customer requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Auto-generated code using model More ❯
watford, hertfordshire, east anglia, united kingdom
Morson Talent
Luton, Bedfordshire. The Firmware Engineer will deliver Firmware for complex digital systems that meet challenging future customer requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Auto-generated code using model More ❯
time effectively. Ownership and responsibility for resolving issues promptly. Desirable Skills: Experience with Vivado, Libero, and Quartus tool chains. Knowledge of Verilog, System Verilog, and cryptographic algorithms. Familiarity with UVM/OSVVM or Assertion Based Verification for design validation. Understanding of Network Layer 2 and Layer 3 protocols, USB 3.2, and NVMe interfaces. Previous experience with high-speed and ultra More ❯
Luton, Bedfordshire. The Firmware Engineer will deliver Firmware for complex digital systems that meet challenging future customer requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7 click apply for full job details More ❯
A leading Defence organisation are seeking multiple Firmware Engineers/FPGAEngineers on 12 month contracts (OutsideIR35) in Edinburgh tobe involved with FPGA firmware development across the Radar and Advanced Targeting line of business, working as part of a larger, multi More ❯
Southampton, Hampshire, South East, United Kingdom Hybrid / WFH Options
Fortis Recruitment Solutions
Hardware Design Engineer , you will: Work closely with algorithm engineers to translate requirements into efficient RTL architectures Design, implement, and verify complex FPGA and ASIC solutions Develop and deploy UVM-based testbenches for functional verification Validate and integrate your designs on the latest FPGA platforms Optimise timing, power, and area for high-throughput digital signal processing applications Contribute to architecture … skills (design specs, verification plans, user guides) Desirable: Knowledge of communications signal processing algorithms (e.g. error correction, equalisation, beamforming, channel estimation) Familiarity with AMBA bus protocols Practical experience with UVMverification methodologies C++/SystemC experience for modelling and integration Scripting skills (Python, Tcl, Bash) for automation and flows Understanding of project methodologies (agile, waterfall, requirements traceability) Experience with AMD More ❯
portsmouth, hampshire, south east england, united kingdom Hybrid / WFH Options
Fortis Recruitment Solutions
Hardware Design Engineer , you will: Work closely with algorithm engineers to translate requirements into efficient RTL architectures Design, implement, and verify complex FPGA and ASIC solutions Develop and deploy UVM-based testbenches for functional verification Validate and integrate your designs on the latest FPGA platforms Optimise timing, power, and area for high-throughput digital signal processing applications Contribute to architecture … skills (design specs, verification plans, user guides) Desirable: Knowledge of communications signal processing algorithms (e.g. error correction, equalisation, beamforming, channel estimation) Familiarity with AMBA bus protocols Practical experience with UVMverification methodologies C++/SystemC experience for modelling and integration Scripting skills (Python, Tcl, Bash) for automation and flows Understanding of project methodologies (agile, waterfall, requirements traceability) Experience with AMD More ❯
Development Verification Engineer £55,000 - £65,000 + Training + Progression + 10% Bonus Bristol - Hybrid Are you a Development Verification Engineer or similar with expertise in SystemVerilog and UVM, seeking an autonomous role where your work directly contributes to the success of a leading semiconductor company, with opportunities for career growth, ongoing development, and the potential to increase your … in the billions and a strong global presence, they support clients in driving efficiency, safety, and sustainability across critical industries. In this role, you will develop and maintain SystemVerilog, UVM test benches, create new verification components, debug test cases, define functional coverage models, while supporting test bench architecture and design reviews using industry standard EDA tools. This is a full … time role, Monday to Friday, 09:00AM - 17:00PM, with two days per week working from home. This role would suit a Development Verification Engineer with SystemVerilog and UVM skills, looking to join a world-leading semiconductor company with clear progression, specialist training, and the opportunity to boost earnings through a company bonus. The Role: Take the lead in creating More ❯
Employment Type: Permanent
Salary: £55000 - £65000/annum Training + Progression + 10% Bonus
Bristol, Avon, South West, United Kingdom Hybrid / WFH Options
Ernest Gordon Recruitment
Development Verification Engineer £55,000 - £65,000 + Training + Progression + 10% Bonus Bristol - Hybrid Are you a Development Verification Engineer or similar with expertise in SystemVerilog and UVM, seeking an autonomous role where your work directly contributes to the success of a leading semiconductor company, with opportunities for career growth, ongoing development, and the potential to increase your … in the billions and a strong global presence, they support clients in driving efficiency, safety, and sustainability across critical industries. In this role, you will develop and maintain SystemVerilog, UVM test benches, create new verification components, debug test cases, define functional coverage models, while supporting test bench architecture and design reviews using industry standard EDA tools. This is a full … time role, Monday to Friday, 09:00AM - 17:00PM, with two days per week working from home. This role would suit a Development Verification Engineer with SystemVerilog and UVM skills, looking to join a world-leading semiconductor company with clear progression, specialist training, and the opportunity to boost earnings through a company bonus. The Role: Take the lead in creating More ❯
Bristol, Avon, South West, United Kingdom Hybrid / WFH Options
Ernest Gordon Recruitment
and Progression) £30,000 - £35,000 + Training + Progression + 10% Bonus Bristol - Hybrid Are you an aspiring Verification Engineer looking to grow your expertise in SystemVerilog and UVM within a world-leading semiconductor company offering industry-leading training, structured progression, and the opportunity to increase your earnings through a 10% company bonus? This leading semiconductor and microcontroller provider … presence, they support clients in driving efficiency, safety, and sustainability across critical industries. In this role, you'll work closely with experienced verification engineers to develop and maintain SystemVerilog - UVM test benches, assist in creating and integrating new verification components and debugging test cases. You'll receive hands-on training, tailored development plans, and support to enhance your technical expertise … time role, Monday to Friday, 09:00AM - 17:00PM, with two days per week working from home. This position would suit an aspiring Verification Engineer with foundational SystemVerilog and UVM knowledge, looking to join a global semiconductor leader that prioritises growth, professional development, and long-term career progression and the opportunity to boost earnings through a company bonus. The Role More ❯
verify FPGA and ASIC IP using Verilog/SystemVerilog Validate and integrate designs on the latest FPGA development platforms Collaborate across architecture, verification, and physical implementation teams Contribute to UVM test environments and technical documentation Key skills required for the FPGA Engineer: Strong RTL experience (Verilog/SystemVerilog) targeting FPGAs or ASICs Skilled in timing closure, synthesis, and power/… resource optimisation Experience working on high-throughput digital signal processing blocks Familiarity with communications algorithms (e.g. FEC, beamforming) is a bonus Knowledge of UVM, scripting (Python), or AMBA protocols is desirable If you’re interested in the position of FPGA Engineer, please apply or contact Sam Cruse. More ❯
Cambridge, Cambridgeshire, England, United Kingdom
MicroTECH Global Ltd
cores, OTBN (cryptographic CPU), AES accelerators, and peripherals like USB, I2C, and SPI. Key Responsibilities Design, implement, and debug block/system-level tests and testbenches using SystemVerilog and UVM Develop test and coverage plans for new and updated designs Triage and debug nightly regressions Review contributions to open-source projects Enhance test and CI infrastructure Collaborate on academic/… industry publications Stay current with verification best practices and introduce improvements Candidate Requirements Essential: 5+ years industry experience in design verification Strong SystemVerilog and UVM expertise Experience across the full verification cycle (planning to tape-out) Able to provide estimates and coordinate with project managers Comfortable in multidisciplinary, multi-organisation teams Familiar with Git and code review tools (GitHub, GitLab More ❯
Bristol, Gloucestershire, United Kingdom Hybrid / WFH Options
Ernest Gordon Recruitment Limited
Development Verification Engineer 55,000 - 65,000 + Training + Progression + 10% Bonus Bristol - Hybrid Are you a Development Verification Engineer or similar with expertise in SystemVerilog and UVM, seeking an autonomous role where your work directly contributes to the success of a leading semiconductor company, with opportunities for career growth, ongoing development, and the potential to increase your … in the billions and a strong global presence, they support clients in driving efficiency, safety, and sustainability across critical industries. In this role, you will develop and maintain SystemVerilog, UVM test benches, create new verification components, debug test cases, define functional coverage models, while supporting test bench architecture and design reviews using industry standard EDA tools. This is a full … time role, Monday to Friday, 09:00AM - 17:00PM, with two days per week working from home. This role would suit a Development Verification Engineer with SystemVerilog and UVM skills, looking to join a world-leading semiconductor company with clear progression, specialist training, and the opportunity to boost earnings through a company bonus. The Role: Take the lead in creating More ❯
reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVMverification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. … concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVMmethodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. Excellent communication skills and a More ❯
reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVMverification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. … concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVMmethodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. Excellent communication skills and a More ❯
reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVMverification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. … concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVMmethodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. Excellent communication skills and a More ❯
reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVMverification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. … concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVMmethodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. Excellent communication skills and a More ❯