1 to 25 of 266 Verilog Jobs

ARM SOC FPGAs (e.g., Xilinx MPSOC) and/or ASICs. You will also write and debug tests and sequences for end-to-end simulation on UVM framework with System Verilog Assertions, as well as C++ based software-driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux. The ideal candidate is passionate about digital design, has excellent analytical and debugging … and integration targeting ARM SOC FPGAs (e.g., Xilinx MPSOC) and/or ASICs. Write and debug tests/sequences for end-to-end simulation on UVM framework with System Verilog Assertions. Develop and debug C++ based software-driven validation on SOC evaluation boards running Linux. Utilize state-of-the-art EDA tools and methodologies for design implementation and verification. Collaborate … team environment while also being self-directed. Nice-to-Haves Prior experience with High Level Synthesis (HLS) with Vivado. Knowledge of Embedded Software C++ (OOP). Experience with System Verilog Assertions (SVA). Familiarity with high-speed protocols (PCIe, TCP/IP, Ethernet). Experience with UVM-based verification environments. Knowledge of ARM-based SoC architectures. Master of Science in More ❯

in Python and TCL would be advantageous. Detailed knowledge of the FPGA design flow from RTL design, simulation, synthesis, place & route, constraints, and timing closure Strong RTL skills in Verilog/System Verilog or VHDL with source code under version control. Scripting skills in Python basic level C/C++. Knowledge and expertise in debugging designs in both simulation and More ❯

in Python and TCL would be advantageous. Detailed knowledge of the FPGA design flow from RTL design, simulation, synthesis, place & route, constraints, and timing closure Strong RTL skills in Verilog/System Verilog or VHDL with source code under version control. Scripting skills in Python basic level C/C++. Knowledge and expertise in debugging designs in both simulation and More ❯

MPSOC) AND/OR ASICs. • Additionally, S/He will be responsible for writing/debugging tests/sequences for End-to-End simulation on UVM framework, with System Verilog Assertions, and writing/debugging C++ based SW driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux. Prefer skills: • High Level Synthesis (HLS) with Vivado, • Embedded SW C++ (OOP … and System Verilog Assertions (SVA) • Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet) • Deployed state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA including HLS, Mentor Questa family, VIPs for UVM, Clock Domain Crossing (CDC), Catapult (HLS). The ideal candidate will have: • Bachelor of Science More ❯

MPSOC) AND/OR ASICs. Additionally, S/He will be responsible for writing/debugging tests/sequences for End-to-End simulation on UVM framework, with System Verilog Assertions, and also writing/debugging C++ based SW driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux. L3T has deployed state-of-the-art EDA flows/methodologies … Debug skills • Good verbal, written, and presentation skills • US Citizenship required A PLUS for prior experience with: • High Level Synthesis (HLS) with Vivado, • Embedded SW C++ (OOP) and System Verilog Assertions (SVA) • Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet More ❯

and testing . Ready to make your mark in the world of FPGA design? Apply now! Desired Skills and Experience FPGA Design, VHDL, Simulink, Xilinx, Intel, Microsemi devices, System Verilog, UVM test-bench, QuestaSim and ModelSim More ❯

and testing . Ready to make your mark in the world of FPGA design? Apply now! Desired Skills and Experience FPGA Design, VHDL, Simulink, Xilinx, Intel, Microsemi devices, System Verilog, UVM test-bench, QuestaSim and ModelSim More ❯

environment where engineers work across the full development flow, and where technical ownership is both expected and supported. What they’re looking for: Proven expertise in RTL design using Verilog or SystemVerilog for complex FPGA or ASIC systems Strong grasp of synthesis, timing closure, and resource optimisation for high-speed signal processing applications Experience developing and integrating IP in multi More ❯

environment where engineers work across the full development flow, and where technical ownership is both expected and supported. What they’re looking for: Proven expertise in RTL design using Verilog or SystemVerilog for complex FPGA or ASIC systems Strong grasp of synthesis, timing closure, and resource optimisation for high-speed signal processing applications Experience developing and integrating IP in multi More ❯

design team (electrical engineers, systems engineers, and scientists) to implement and integrate FPGA designs and sensor systems. Analyze, design, simulate, and implement algorithms in hardware descriptor languages, HDL (VHDL, Verilog), based on MATLAB model(s). Analyze, design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation and validation against models. Analyze schematic diagrams More ❯

future customer requirements. Your role may involve travel across the UK or abroad for technical reviews. What we need from you Essential requirements: Design tools such as Xilinx, TCL, Verilog, System Verilog, and UVM FPGA architectures like Xilinx 7, Xilinx UltraScale, Intel (Altera), or Microsemi (Actel) Fast interfaces such as PCIe, Ethernet, and JESD Auto-generated code using model-driven More ❯

challenging future customer requirements. Your role may even take you across the UK or abroad for technical reviews. What we need from you Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Auto More ❯

FPGA/Firmware delivery teams What we need from you What you really must have: Experience leading teams or managing packages of work. Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Auto More ❯

field 10+ years' experience in complex SOCs Deep understanding of Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, eFuse) Extensive experience with the Digital ASIC Flow, RTL design (Verilog), synthesis, timing closure, and debug methodologies (e.g., DFT, JTAG, Scan, BIST). Extensive knowledge of SOC architecture, setup/silicon bring-up, validation, and all associated processes. SOC design, system More ❯

Commercial and business awareness Experience of working across the full life cycle Familiarity with latest FPGA device families and verification methodologies Proven expertise of developing FPGA using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design flows (ISE, Vivado, Quartus) and More ❯

agency recognized by the US Secretary of Education. • Digital system partitioning and advanced function implementation in FPGAs. • Solid electronic circuit design and electronic systems background. • Expertise in VHDL/Verilog and System Verilog. • Experience with FPGA design tools including Xilinx Vivado/Vitis and Mentor Modelsim/Questasim. • Ability to work requirements and flow down for system/subsystem/ More ❯

developed prototype systems in the laboratory and/or the field to internal Kirintec teams and to Kirintec’s customers/partners. Essential Skills FPGA design experience using VHDL. Verilog design experience not essential but must be able to integrate/debug third party design components written in Verilog. Designing pipelined Digital Signal Processing blocks in FPGA. Writing automated VHDL More ❯

will be responsible for: - Hardware requirements capture and management. - Concept development for complex functions and systems. - FPGA design and analysis. - Experience in verification techniques using either VHDL or System Verilog/UVM. - Production of material for design reviews. - Development of test planning, integration and design verification. - Ensure that all firmware designs follow the company firmware process. - Experience using FPGA technologies More ❯

This job is brought to you by Jobs/Redefined, the UK's leading over-50s age inclusive jobs board. £65-80K - Full-time - London/Hybrid IONATE is a deep technology start-up building the technology backbone for More ❯

RBR-Technologies is a small service-disabled veteran-owned information and technology business founded on the basic principle of delivering customer mission success. RBR-technologies prides itself on our commitment to mission success as exemplified by the trust our customers More ❯

UK office. Your CV will show your: Good degree in electronics or another technical subject from a top university Extensive experience developing complex and well-structured RTL in SystemVerilog, Verilog or VHDL, with particular attention to design approach and performance constraints And as a skilled FPGA Design Engineer you will also have, as your CV demonstrates: A strong understanding of More ❯

Verifying firmware designs Ensuring configuration management/keeping designs under revision control Providing progress reports Skills, Qualifications and Experience required: Mandatory Proven expertise of developing firmware using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design flows (ISE, Vivado, Quartus) and More ❯

back into the ASIC. Model algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence through to gate‐level sign‐off. Own RTL development (SystemVerilog/Verilog/VHDL) including synthesis, static‐timing closure, formal and constrained‐random verification. Analyse power, performance and area (PPA); implement innovative techniques to achieve aggressive bandwidth‐per‐watt targets. Collaborate with More ❯

tools including Lint, CDC, Synthesis, Power analysis tools. Planning, reporting status and communicating progress against expectations. Required Competencies Effective communicator with strong technical presentation skills. RTL design in System Verilog and expert digital design knowledge. Able to work autonomously and demonstrate technical competency. Knowledge of DSP design for Audio signal processing. Knowledge of power reduction techniques (DVFS, power gating, DMA More ❯

tools including Lint, CDC, Synthesis, Power analysis tools. Planning, reporting status and communicating progress against expectations. Required Competencies Effective communicator with strong technical presentation skills. RTL design in System Verilog and expert digital design knowledge. Able to work autonomously and demonstrate technical competency. Knowledge of DSP design for Audio signal processing. Knowledge of power reduction techniques (DVFS, power gating, DMA More ❯