20 of 20 Remote UVM Jobs

Science. 3+ years of experience as a Verification Engineer with FPGA's or equivalent is a must have. Extensive experience with System Verilog and UVM is a must have Understanding of VHDL/Verilog Designs is a must have. Experience with Assertion Based Verification (SVA especially, PSL) is preferred Broad More ❯

Science. 3+ years of experience as a Verification Engineer with FPGA's or equivalent is a must have. Extensive experience with System Verilog and UVM is a must have Understanding of VHDL/Verilog Designs is a must have. Experience with Assertion Based Verification (SVA especially, PSL) is preferred Broad More ❯

hardware verification languages e.g. (SystemVerilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.). Experienced in one or more of various verification methodologies - UVM/OVM, formal, low power, emulation. Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case More ❯

You have experience with EDA tools for simulation, code coverage analysis, synthesis, formal verification and linting. You have experience with verification flows and building UVM-based testbenches. You have experience in simulating RTL and netlists with annotated timing. You are familiar with scripting tools like Python and TCL for automation More ❯

Lead FPGA/Firmware Engineer Apply locations GB - Luton - Cap. Green 300 time type Full time posted on Posted 30+ Days Ago job requisition id R Job Description: Would you like to deliver the complex Firmware that forms part of More ❯

Firmware Engineer - All levels Firmware Engineer - All levels Apply locations: GB - Edinburgh, GB - Newcastle Time type: Full time Posted on: Posted Yesterday Job requisition id: R Job Description: The opportunity: We are looking for a wide range of Firmware Engineers More ❯

Job Description: The opportunity: We are looking for a wide range of Firmware Engineers at various levels to join Leonardo in Edinburgh and Newcastle. Leonardo is a world-class defence technology company. We develop cutting-edge Radars for the Eurofighter More ❯

performance bugs. Proficiency with EDA tools (Candence, Mentor) and design languages including Verilog and systemVerilog Understanding of synthesis, static timing analysis, and netlist verifications UVM expertise Please note: You must have full UK working rights to be considered for this role. For more information, please contact Rachel Mason at IC More ❯

Are you ready to shape the future of cutting-edge technology? Leonardo, a global leader in advanced electronics, is seeking Firmware/FPGA Engineers at various levels to join our innovative teams across the UK. We are proud to welcome More ❯

to emulation Knowledge of TBX, ICE and co-model solutions Highly proficient in HDLs (Verilog/SV) for RTL design and HVLs (SV/UVM) for verification Solid background in Functional Verification, RTL synthesis and PnR flows Conversant with SoC design and architecture concepts Desirable Competencies Familiarity with Data Centre … USB, DDR, DisplayPort, etc. Commercial awareness of EDA companies and solutions Linux, Tcl/Python/shell, C/C++, DPI, SCE-MI, SystemC, UVM Connect, UVM Framework Background in consulting or other customer services subject area About You BSc/MSc qualified in Electronic Engineering, Computer Engineering or Computer More ❯

high-performing, and built to scale. What you will be doing: • Creating and executing thorough verification plans for complex hardware designs • Developing SystemVerilog/UVM testbenches for functional verification • Running directed and constrained-random tests • Maintaining regression suites to validate design quality • Supporting system-level performance validation • Debugging design issues … Using formal verification techniques when appropriate Requirements: • 5+ years of hands-on experience in hardware verification (preferably in SoCs) • Strong skills in SystemVerilog and UVM • Experience with modern verification tools (ABV, CDV, etc.) • Bonus: Experience with GPU, vector processors, or AI accelerators • Bonus: Familiarity with RISC-V architecture • Strong debugging More ❯

high-performing, and built to scale. What you will be doing: • Creating and executing thorough verification plans for complex hardware designs • Developing SystemVerilog/UVM testbenches for functional verification • Running directed and constrained-random tests • Maintaining regression suites to validate design quality • Supporting system-level performance validation • Debugging design issues … Using formal verification techniques when appropriate Requirements: • 5+ years of hands-on experience in hardware verification (preferably in SoCs) • Strong skills in SystemVerilog and UVM • Experience with modern verification tools (ABV, CDV, etc.) • Bonus: Experience with GPU, vector processors, or AI accelerators • Bonus: Familiarity with RISC-V architecture • Strong debugging More ❯

About Us Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop new and highly innovative electronic products faster and more cost-effectively. Our customers use our tools More ❯

About Us Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop new and highly innovative electronic products faster and more cost-effectively. Our customers use our tools More ❯

considered) Contract : Contract | Outside IR35 Hourly Rate : Negotiable What You will Do: Develop verification plans for complex hardware designs Create and run SystemVerilog/UVM testbenches Support performance validation and debug issues Use formal verification techniques as needed Requirements: 5+ years of experience in hardware verification (preferably SoCs) Strong skills … in SystemVerilog and UVM Familiarity with GPU , AI accelerators , or RISC-V (bonus) Experience with scripting languages (Python, Perl, TCL) Why Join? Work on cutting-edge GPU and AI projects Be part of an innovative and flexible team If you are interested, please send me your CV. Feel free to More ❯

Staff level - IP Level/Unit Level verification experience is a must - Experience in designing verification environments for RTL designs - Experience with SystemVerilog and UVM - Understanding of end to end verification processes - UVM knowledge is a bonus - Understanding of computer architecture, such as pipelining, memory systems etc are a bonus More ❯

Staff level - IP Level/Unit Level verification experience is a must - Experience in designing verification environments for RTL designs - Experience with SystemVerilog and UVM - Understanding of end to end verification processes - UVM knowledge is a bonus - Understanding of computer architecture, such as pipelining, memory systems etc are a bonus More ❯

Staff level - IP Level/Unit Level verification experience is a must - Experience in designing verification environments for RTL designs - Experience with SystemVerilog and UVM - Understanding of end to end verification processes - UVM knowledge is a bonus - Understanding of computer architecture, such as pipelining, memory systems etc are a bonus More ❯

Staff level - IP Level/Unit Level verification experience is a must - Experience in designing verification environments for RTL designs - Experience with SystemVerilog and UVM - Understanding of end to end verification processes - UVM knowledge is a bonus - Understanding of compute... More ❯

UCIe, NVMe, Ethernet, USB, DDRx, HBM, AMBA. Knowledge of controllers for one or more high-speed interface protocols Expertise in coding with SystemVerilog, and UVM is mandatory Experience with integrating commercial VIP in SV/UVM bench required. Experience with Linux and Windows environments including scripting languages. Individual leadership and More ❯