2 of 2 SystemVerilog Jobs in Central London

testbench issues efficiently. At least two years of professional RTL functional verification experience for FPGA or ASIC designs. Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis. Proficiency in Python and/or C++ for building verification infrastructure, tooling, and automation. ...

ASIC Design Engineer Location: London or UK Remote I am seeking an ASIC Design Engineer to join a rapidly growing scale-up at the forefront of hardware security for AIoT. This is a business-critical ...