17 of 17 Synopsys Jobs in the East of England

and methodologies to improve GPU power, performance and area (PPA). Required Skills and Experience : Experience with hardware description languages (System Verilog preferable). Experience using EDA simulators (Siemens, Synopsys, Cadence) Strong problem solving and debugging skills, and ability to closely collaborate with other teams. Experience working with version control and code review systems such as Git and Gerrit Proficiency More ❯

SoCs. Partner with cross-functional teams to enable system bring-up, debug, and feature validation on emulation platforms. Support compilation, deployment, and debug flows for emulation systems such as Synopsys ZeBu, Cadence Palladium, and Siemens Strato. Solve simulation/emulation mismatches and system-level test failures. Work closely with EDA vendors to deploy new capabilities, resolve tool issues, and influence More ❯

ability to closely collaborate with hardware and software teams. Good written and verbal communication skills. Experience with hardware description languages (System Verilog preferable). Experience using EDA simulators (Siemens, Synopsys, Cadence) Experience working with version control and code review systems such as Git and Gerrit Experience with scripting languages such as Python, Perl, JSON, Tcl, Make etc. Motivated, dedicated and More ❯

and advance PPA. Key Requirements: 8+ years of experience within Physical Design, ideally with exposure to low-power design techniques. Experience with Cadence (Genus, Innovus, Tempus, QRC, Conformal) and Synopsys (Fusion Compiler, Formality) tools. Understanding in building flows and methodology using scripting languages such as TCL, Python, Perl to support project development. More ❯

verification. Proficiency in RTL design techniques, including synthesis, timing closure, and verification. Experience in using UVM for functional verification of ASIC designs. Experience with EDA tools like Cadence and Synopsys for design simulation and verification. Extensive experience with FPGA emulation, design tools, and verification. Contact: For further information please contact Mícheál at Software Placements on 00353 1 or email More ❯

environment. "Nice To Have" Skills and Experience : Experience with SoC-level build and integration flows, including flow optimization and maintenance. Solid understanding of industry-standard EDA tools such as Synopsys, Cadence, and Mentor. Exposure to design databases for storing, managing, and retrieving build logs and verification results. Familiarity with data representation formats such as YAML and JSON, and markup languages More ❯

scheduling of own work inline with the project goals and needs. Experience Cadence: Genus, Innovus, Tempus, QRC & Conformal PnR Flow: Synthesis, LEC, CLP, Floorplan, Placement, CTS, PostCTS, Routing, STA Synopsys: Fusion compiler, Formality Synthesis, LEC Low power design techniques (power gating, DVFS etc.) Understanding in building flows and methodology using scripting languages such as TCL, Python, Perl to support project More ❯

with the project goals and needs. What you'll need to succeed Cadence: Genus, Innovus, Tempus, QRC & Conformal PnR Flow: Synthesis, LEC, CLP, Floorplan, Placement, CTS, PostCTS, Routing, STA Synopsys: Fusion compiler, Formality Synthesis, LEC Low power design techniques (power gating, DVFS etc.) Understanding in building flows and methodologies using scripting languages such as TCL, Python, Perl to support project More ❯

UK or abroad for technical reviews. What we need from you You should have experience in most of the below Design techniques using one or more of VPI, Ansys, Synopsys or similar simulation tool. Physical realisation of Photonics circuits or spread benches Derivation of and reporting against design requirements A structured approach to design Photonic test methods and equipment. Including More ❯

tools desired. Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, Cell Aware etc. Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other state of the art EDA tools. Experience in MBIST implementation and verification will be a strong plus. Good understanding of STA concepts having handled DFT … timing closure before would be a plus. Experience in Spyglass based DFT DRC checks at RTL level would be a plus. Experience with Synopsys Design Compiler/Test Compiler/Fusion Compiler etc would be a plus. Prior experience in working with Version control systems like perforce, git etc would be critical. Understanding of Logic Equivalence, CDC, Lint, UPF/ More ❯

as Genus, Innovus, Tempus, QRC, and Conformal. Proficient in physical design flows including synthesis, logical equivalence checking (LEC), floorplanning, placement, clock tree synthesis (CTS), routing, and STA. Familiarity with Synopsys Fusion Compiler and Formality tools. Knowledge of low power design methodologies including power gating and dynamic voltage and frequency scaling (DVFS). Ability to develop and maintain automation scripts using … Physical Design, RTL, Place and Route (PnR), Static Timing Analysis (STA), Logical Equivalence Checking (LEC), Low Power Design, Power Gating, DVFS, Cadence Genus, Cadence Innovus, Cadence Tempus, QRC, Conformal, Synopsys Fusion Compiler, Formality, Synthesis, Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, UPF, Constraint Development, EDA Tools, Automation Scripting, TCL, Python, Perl, Semiconductor, GPU Design If you are interested in this More ❯

precision bias circuits and fractional-N PLLs to support system-level integration. Work with SiGe and CMOS process technologies to achieve optimal analogue performance. Use industry-standard tools (Cadence, Synopsys) for schematic entry, layout supervision, and verification. Collaborate with layout engineers, validation teams, and system architects to ensure successful silicon implementation and debug. Qualifications and Skills required for this Senior … Design, or a related field, with extensive experience in IC design. Strong background in analogue circuit design including references, PLLs, and passive/active filters. Experience with Cadence or Synopsys tool suites for design and verification. Familiarity with SiGe and CMOS technology platforms. Good understanding of analogue performance metrics such as linearity, PSRR, and noise. Effective communicator and team player More ❯

precision bias circuits and fractional-N PLLs to support system-level integration. Work with SiGe and CMOS process technologies to achieve optimal analogue performance. Use industry-standard tools (Cadence, Synopsys) for schematic entry, layout supervision, and verification. Collaborate with layout engineers, validation teams, and system architects to ensure successful silicon implementation and debug. Qualifications and Skills required for this Senior … Design, or a related field, with extensive experience in IC design. Strong background in analogue circuit design including references, PLLs, and passive/active filters. Experience with Cadence or Synopsys tool suites for design and verification. Familiarity with SiGe and CMOS technology platforms. Good understanding of analogue performance metrics such as linearity, PSRR, and noise. Effective communicator and team player More ❯

precision bias circuits and fractional-N PLLs to support system-level integration. Work with SiGe and CMOS process technologies to achieve optimal analogue performance. Use industry-standard tools (Cadence, Synopsys) for schematic entry, layout supervision, and verification. Collaborate with layout engineers, validation teams, and system architects to ensure successful silicon implementation and debug. Qualifications and Skills required for this Senior … Design, or a related field, with extensive experience in IC design. Strong background in analogue circuit design including references, PLLs, and passive/active filters. Experience with Cadence or Synopsys tool suites for design and verification. Familiarity with SiGe and CMOS technology platforms. Good understanding of analogue performance metrics such as linearity, PSRR, and noise. Effective communicator and team player More ❯

by delivering high-performance RFIC solutions. Design and simulate key RFIC building blocks including amplifiers, mixers, and oscillators. Carry out schematic capture, layout supervision, and verification using Cadence or Synopsys tools. Perform EM simulation and optimisation using tools such as ADS or Momentum. Work with cross-functional teams on block and system-level integration to ensure robust performance. Contribute to … for this Senior RFIC Design Engineer job, based in Maldon: Degree in Electronics, RFIC Design, or a related field, with extensive experience in RFIC development. Proficiency in Cadence or Synopsys design environments, including schematic, layout, and verification workflows. Experience with EM simulation tools (e.G., ADS, Momentum) and understanding of RF metrics like gain, NF, linearity, and phase noise. Familiarity with More ❯

by delivering high-performance RFIC solutions. Design and simulate key RFIC building blocks including amplifiers, mixers, and oscillators. Carry out schematic capture, layout supervision, and verification using Cadence or Synopsys tools. Perform EM simulation and optimisation using tools such as ADS or Momentum. Work with cross-functional teams on block and system-level integration to ensure robust performance. Contribute to … for this Senior RFIC Design Engineer job, based in Maldon: Degree in Electronics, RFIC Design, or a related field, with extensive experience in RFIC development. Proficiency in Cadence or Synopsys design environments, including schematic, layout, and verification workflows. Experience with EM simulation tools (e.G., ADS, Momentum) and understanding of RF metrics like gain, NF, linearity, and phase noise. Familiarity with More ❯

by delivering high-performance RFIC solutions. Design and simulate key RFIC building blocks including amplifiers, mixers, and oscillators. Carry out schematic capture, layout supervision, and verification using Cadence or Synopsys tools. Perform EM simulation and optimisation using tools such as ADS or Momentum. Work with cross-functional teams on block and system-level integration to ensure robust performance. Contribute to … for this Senior RFIC Design Engineer job, based in Maldon: Degree in Electronics, RFIC Design, or a related field, with extensive experience in RFIC development. Proficiency in Cadence or Synopsys design environments, including schematic, layout, and verification workflows. Experience with EM simulation tools (e.G., ADS, Momentum) and understanding of RF metrics like gain, NF, linearity, and phase noise. Familiarity with More ❯