9 of 9 Synopsys Jobs in Cambridgeshire

UVM (Universal Verification Methodology) and coverage-driven verification Skilled in analyzing waveforms, simulation outputs, and debugging complex digital behaviors Synthesis, Implementation & File Generation Proficient in synthesis and implementation using: Synopsys Design Compiler Cadence Genus Xilinx Vivado Intel Quartus Prime Experienced in generating and managing key implementation deliverables: .lib files for timing and cell characterization .lef files for physical abstraction of … Test Pattern Generation (ATPG) and analyzing test coverage reports Understanding of DFT constraints and impact on design timing and area Tools & Workflow Automation Experienced with industry-standard EDA tools : Synopsys, Cadence, Siemens/Mentor, Xilinx, Intel Proficient in version control systems such as Git for collaborative development Skilled in scripting and workflow automation using Python , TCL , Make , and Shell scripting More ❯

tools desired. Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, Cell Aware etc. Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other state of the art EDA tools. Experience in MBIST implementation and verification will be a strong plus. Good understanding of STA concepts having handled DFT … timing closure before would be a plus. Experience in Spyglass based DFT DRC checks at RTL level would be a plus. Experience with Synopsys Design Compiler/Test Compiler/Fusion Compiler etc would be a plus. Prior experience in working with Version control systems like perforce, git etc would be critical. Understanding of Logic Equivalence, CDC, Lint, UPF/ More ❯

and methodologies to improve GPU power, performance and area (PPA). Required Skills and Experience : Experience with hardware description languages (System Verilog preferable). Experience using EDA simulators (Siemens, Synopsys, Cadence) Strong problem solving and debugging skills, and ability to closely collaborate with other teams. Experience working with version control and code review systems such as Git and Gerrit Proficiency More ❯

SoCs. Partner with cross-functional teams to enable system bring-up, debug, and feature validation on emulation platforms. Support compilation, deployment, and debug flows for emulation systems such as Synopsys ZeBu, Cadence Palladium, and Siemens Strato. Solve simulation/emulation mismatches and system-level test failures. Work closely with EDA vendors to deploy new capabilities, resolve tool issues, and influence More ❯

Overview: Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to More ❯

Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. (PLUS) Proven experience with formal verification tools (e.g., Cadence JasperGold, Synopsys VC Formal, or equivalent tools). Hands-on experience with RTL design such as Verilog, SystemVerilog, or VHDL. Experience with verification methodologies such as UVM (Universal Verification Methodology) or other More ❯

within ASIC or SoC development flows. Hands-on expertise in scan stitching, ATPG, boundary scan, on-chip clocking , and DFT partitioning . Proficient in using modern DFT tools (e.g., Synopsys, Cadence, or Mentor platforms). Solid understanding of RTL design , STA , and silicon test methodologies . A proactive, solution-oriented mindset and excellent collaboration skills. For more information please contact More ❯

Fixed-term: The funds for this post are available until 30 September 2027. Applications are invited for a full-time Research Assistant/Associate to work on the design and implementation of next-generation AI hardware (ASIC) accelerators. The UK More ❯

Fixed-term: The funds for this post are available until 30 September 2027. Applications are invited for a full-time Research Assistant/Associate to work on the design and implementation of next-generation AI hardware (ASIC) accelerators. The UK More ❯