26 to 50 of 55 SystemVerilog Jobs in England

Firmware (FPGA) Engineer Become a key part of a team with a proven track record for delivering firmware for a wide range of defence, related products. Typical firmware services provided: - Architecture, requirements specification, design, verification ...

London. The role involves delivering emulation capabilities for GPU designs while collaborating with design and software teams. Candidates should have strong knowledge in SystemVerilog, debugging skills, and proficiency in programming languages such as Python, C, and C++. The position offers the opportunity to innovate and be part of a dynamic ...

level assembly, and collaborate with graphics architecture, verification, and physical design teams to meet performance and power goals. The role requires deep SystemVerilog/VHDL expertise, strong problem-solving skills, and experience with large-scale SoC or GPU design. #J-18808-Ljbffr ...

seeking penultimate or final-year students or graduates to join the FPGA team. You will design and optimise ultra-low-latency FPGA pipelines, using SystemVerilog and high-performance languages to ship real market-facing code. We value curiosity, practical software and hardware work, and the ability to work across hardware ...

Debug and analyse top-level design issues Codeline management, supporting multiple products & chips Review RTL implementations and mentor junior engineers Minimum Qualifications Expertise in SystemVerilog/VHDL and proficiency in revision control systems Strong problem-solving skills, ability to work across team boundaries and be productive under aggressive schedules Preferred ...

/emulation mismatches and test failures. Hands-on experience with emulation platforms such as ZeBu, Palladium, or Strato. Familiarity with RTL languages such as SystemVerilog/VerilogExperience in collaboration with EDA vendors to introduce new capabilities, resolve tool issues, and contribute to future tool improvements. Skilled in planning system test ...

incident response workflows for Fractile's infrastructure. IaC TODO Scale and maintain Fractile's Bazel monorepo as we continue growing across Python, C++, Rust, SystemVerilog, and ML workloads. Shape the infrastructure and platform experience for every engineer at Fractile. About You You bring deep infrastructure and build systems expertise alongside ...

stack is, in fact, in Java). However, once you are here, you will be exposed to a diverse tech stack including Python, TypeScript, SystemVerilog (for FPGAs), Raft, Kubernetes, DLT, Angular, and more. The Package Equity: We offer real equity options. You are building the company’s value ...

The Mission At OQC, we aren’t just theorising about the future; we’re building it. Born from a philosophy of bold innovation, we’ve successfully transitioned quantum computing from an academic dream into a ...

Job Title: FPGA Engineer Location: Basildon, Essex - Hybrid 3+ days on-site per week Role Type : Permanent Salary: £55,000 - £80,000 depending on experience Our client, an established engineering consultancy, require an experienced FPGA ...

tests, and collaborating with teams on high-quality RTL releases. Ideal candidates should have a software mindset to solve hardware problems, strong skills in SystemVerilog, and an eagerness to learn and improve practices within a fast-paced, collaborative environment. #J-18808-Ljbffr ...

tests, and collaborating with teams on high-quality RTL releases. Ideal candidates should have a software mindset to solve hardware problems, strong skills in SystemVerilog, and an eagerness to learn and improve practices within a fast-paced, collaborative environment. #J-18808-Ljbffr ...

Doing Define and optimise capacitive sensing architectures and acquisition strategies Work with the design team to define and verify RTL using Verilog/SystemVerilog Develop high-performance embedded software for sensing and signal-processing functions Drive silicon bring-up, debugging and validation activities Solve complex system-level challenges across analog … related discipline 5+ years’ experience in digital or mixed-signal IC design and development Strong RTL design skills using Verilog and/or SystemVerilog Embedded software development experience in C/C++ Solid understanding of microcontroller architectures and embedded systems Experience using Python, MATLAB or similar tools for modelling, automation ...

doing Designing and developing advanced mixed-signal and embedded solutions Defining digital architectures and contributing to RTL development using Verilog/SystemVerilog Developing embedded software in C/C++ for sensing, control and signal processing applications Supporting silicon bring-up, debugging and validation activities Working across hardware, firmware and system … Contributing to technology and product roadmaps What we're looking for Experience developing digital or mixed-signal integrated circuits Strong Verilog and/or SystemVerilog skills Embedded software development experience using C/C++ Good understanding of microcontrollers and embedded systems Experience with Python, MATLAB or similar engineering tools Strong ...

validation, and product release. Key Responsibilities: System Architecture: Lead FPGA subsystem architecture for complex data platforms. RTL & Verification: Design/verify digital RTL (SystemVerilog/Verilog) using AMD/Xilinx toolchains. Optimization: Maximize throughput, power efficiency, resource usage, and timing closure. Integration: Collaborate with ASIC, FW, and SW teams … automation and mentor mid/senior hardware engineers. What We Need: Proven full-lifecycle FPGA design experience (architecture to hardware bring-up). Strong SystemVerilog/Verilog skills with AMD/Xilinx toolchains (Vivado/Questa). Hands-on experience with high-speed interfaces (PCIe/DMA) and lab debugging ...

methodologies, high-quality deliverables and successful project outcomes. Key Responsibilities Develop and execute verification strategies for complex ASIC and FPGA designs. Create and maintain SystemVerilog/UVM verification environments, testbenches and coverage models. Debug RTL and verification issues, ensuring designs meet quality and performance requirements. Collaborate with design, FPGA … reviews. Essential Skills & Experience Degree in Electronic Engineering, Computer Engineering or a related discipline. Proven experience verifying ASIC and/or FPGA designs. Strong SystemVerilog and UVM expertise. Good understanding of RTL design and digital hardware development. Experience with coverage-driven and assertion-based verification techniques. Linux proficiency and scripting ...

validation, helping ensure high-quality, reliable products. In this role, you will: Design and develop firmware using Hardware Description Languages (VHDL, Verilog, or SystemVerilog) Lead or contribute to firmware architecture and design decisions Verify and validate firmware using simulation and testbench environments Work closely with systems, hardware, and software engineers … operate with a high level of autonomy. You'll bring: Strong experience developing firmware for FPGA-based systems Expertise in VHDL, Verilog, or SystemVerilog Experience with simulation and verification tools (e.g. ModelSim, QuestaSim) Solid understanding of digital design and hardware/software integration Ability to contribute to or lead design ...

cleanly into end-to-end robotics solutions.**Key Responsibilities****FPGA IP Design & Architecture*** Design, implement, and optimize high-performance soft IP in Verilog/SystemVerilog for robotics and industrial solutions* Define and maintain low-level HAL/driver APIs that expose IP capabilities to embedded and host software* Develop … Electrical/Electronic Engineering (EEE), Computer Engineering, Computer Science, or a related discipline* Strong production experience in RTL design (Verilog and/or SystemVerilog) targeting FPGAs* Hands-on experience with RTL verification and simulation (e.g. ModelSim/Questa, VCS, or equivalent)* Proven ability to close timing and optimize resource utilization ...

edge FPGA devices, tuned until there’s nothing left to remove. This is not “hardware vs software.” It’s both, collapsed into one surface. SystemVerilog where cycles are carved out, C++ and Python where control, testing, and orchestration live. The outcome is simple: market data in, decisions out, faster than … problems. Code that ships, signals that route, decisions that execute. Design and optimise FPGA pipelines where latency is measured, hunted, and reduced relentlessly. Use SystemVerilog, C++, and Python to build and validate high-performance systems under real market conditions. Implement and verify features that directly improve market data handling ...

engineering team, contributing to the core FPGA technology that powers a range of next-generation products. Responsibilities Design and develop reusable FPGA modules using SystemVerilog for deployment across multiple products. Perform RTL verification and support timing closure through constraints, analysis, and design optimisation. Write module specifications, review code and documentation … maintain high engineering standards. Collaborate with hardware, software, and mechanical engineers to deliver new products to market. Essential Experience Strong SystemVerilog FPGA design experience. RTL verification skills and familiarity with Python. Experience writing timing constraints and achieving timing closure. Desirable Experience Experience with cocotb for FPGA verification. Familiarity with Linux ...

Degree in Electronic Engineering, Computer Engineering, or a related discipline. At least 3 years' experience verifying digital ASIC and/or FPGA designs. Strong SystemVerilog and UVM experience. Good understanding of RTL design principles and hardware implementation. Experience with coverage-driven and assertion-based verification. Linux proficiency with Python … Ability to collaborate effectively across multiple engineering teams. What You'll Be Doing: Develop verification plans from design and architecture specifications. Create and maintain SystemVerilog/UVM verification environments. Develop testbenches, assertions, scoreboards and coverage models. Carry out directed and constrained-random verification. Analyse coverage and debug RTL and verification ...

FPGA ENGINEER – ULTRA-LOW LATENCY SYSTEMSLocation: London (Hybrid: 4 days onsite)Sector: Quant Trading/High-Performance ComputingQuant Capital is partnering with a global trading firm building a greenfield FPGA team focused on low-latency ...

This is a superb opportunity to join one of the hottest names in the industry! A chance to build a technology that transforms the future of humanity. A chance to work on products that have ...

Job Title: Senior Digital Design Engineer Location: Cambridge, United Kingdom Job Type: Permanent Salary: 65K - 88K GBP per annum DOE Role Overview: Work at the forefront of open silicon and hardware security, contributing to next ...

delivering first-time success with complex mixed-signal ICs Metric-driven verification: planning, requirements extraction, directed & constrained-random verification, functional and code coverage analysis SystemVerilog, including SVA (SystemVerilog Assertions) Testbench design using verification frameworks such as UVM, OVM, e, or VMM Strong RTL/testbench debugging skills (including gate-level ...