1 to 18 of 18 Tcl Jobs in England

of UVM, SVA, VIP, and UPF for digital IC design verification Familiar with Linux OS, revision control like Git and scripting languages like Bash, Tcl, and Python Desirable Skills and Experience Experience with unit test frameworks like pytest, build scripting, Jenkins CI/CD automation Familiar with Xilinx FPGA development more »

and structured approach to problem-solving. RTL skills in Verilog or VHDL. Use of a UNIX environment and shell programming/scripting in e.g. Tcl, Perl, Python etc. Programming languages such as: assembly language, higher-level (e.g. C), object orientated (e.g. C++). If this role is of any interest more »

and structured approach to problem-solving. • RTL skills in Verilog or VHDL • Use of a UNIX environment and shell programming/scripting in e.g. Tcl, Perl, Python etc • Programming languages such as: assembly language (ideally Arm assembler), higher-level (e.g. C), object orientated (e.g. C++) You can reach me on more »

knowledge of on-chip bus protocol (AMBA AHB, APB, AXI-Stream, etc). Experience with Linux OS, revision control (Git) and scripting languages (Bash, Tcl, and Python). Experience with EDA tools for simulation (Siemens Quest), Synthesis (DesignCompiler). Pay rate: Up to £70 ph D.O.E outside IR35 more »

scripting languages, particularly writing, and debugging Linux/Unix bash scripts is an advantage. Knowledge of a programming language such as C, Java, python, TCL, VBA would be useful but not essential. Spacecraft electrical and harness knowledge would be an advantage but not essential. Additional information: This role shall work more »

and UVM test benches Creation of UVM test benches System Verilog assertions Managing regression and debugging failures Scripting languages (e.g. Perl/Python/TCL) As this is a Senior role, team leadership skills will be welcomed and there could be an opportunity to take on more of a ‘lead more »

and ability to travel to customer sites. Preferred Requirements Diverse use of CAE tools across multiple disciplines is a plus. Experience with programming languages (TCL/Python or similar). FEA-based optimisation techniques applied to composite and metallic structures. Experience working in a software company in a Pre-sales more »

techniques Strong knowledge of FPGA tool flows (synthesis, partitioning, place&route, timing analysis) Excellent skills in SystemVerilog/Verilog/VHDL Experience in scripting (tcl preferable) and Python programming Experience using Questa, ModelSim, GHDL, Verilator, cocotb Experience using Quartus/Vivado/Vitis Experience in High Level Synthesis (HLS) Experience more »

Verification methodologies(UVM) , Verification Ips Familiar with Data management and version control systems Proficiency in programming and/or scripting languages (Python, Cshell and TCL) Background in digital circuitry or hardware logic design Able to work autonomously and plan and perform research tasks You have a strong sense of responsibility more »

supply chain management • Linux Operating Systems (Command line interface to administer OS performance, log files navigation and deploy releases) • Proficient using SQL (DML, DDL, TCL) and SQL Developer • Experience with PL/SQL language • Debugging skills • Hands-on database experience (Oracle beneficial) • 1+ years' experience in software application support and more »

Synopsys) STA DFT Test mode timing constraint development and analysis In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools TCL scripting; Python scripting is a plus Bachelor Degree minimum required in Electronics or other related fields more »

their field, using world-class facilities to deliver Firmware for complex digital systems that meet challenging future customer requirements. • Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM • FPGA architectures such as Xilinx 7. Xilinx UltraScale Intel (Altera) or Microsemi (Actel) • Fast interfaces such as PCIe, Ethernet, and more »

digital IF equipment. 3. Produce HDL code for VITA-49 or similar network SDR transport protocols. 4. Expert user of Linux. 5. Scripting in TCL designs utilizing IP Cores for rapid development. 6. Build scripting to support continuous integration. 7. Design and development of test benches to prove Verilog code. more »

digital IF equipment. 3. Produce HDL code for VITA-49 or similar network SDR transport protocols. 4. Expert user of Linux. 5. Scripting in TCL designs utilizing IP Cores for rapid development. 6. Build scripting to support continuous integration. 7. Design and development of test benches to prove Verilog code. more »

digital IF equipment. 3. Produce HDL code for VITA-49 or similar network SDR transport protocols. 4. Expert user of Linux. 5. Scripting in TCL designs utilizing IP Cores for rapid development. 6. Build scripting to support continuous integration. 7. Design and development of test benches to prove Verilog code. more »

digital IF equipment. 3. Produce HDL code for VITA-49 or similar network SDR transport protocols. 4. Expert user of Linux. 5. Scripting in TCL designs utilizing IP Cores for rapid development. 6. Build scripting to support continuous integration. 7. Design and development of test benches to prove Verilog code. more »

Electronics or Electrical Engineering Good understanding of RTL To GDS implementation flow Experience working at 28nm, 16nm, 14nm or 7nm process nodes Experience in TCL, Shell, Python etc Experience in tape out procedures Expertise in Timing constraints and STA Experience in DFT methodologies Email - jordan.browne@ic-resources.com Tel - 01189073075 LinkedIn more »

e, VMM Debugging skills - RTL - Testbench, OOP - Gate level (including SDF) Formal verification and verification qualification techniques Scripting experience with Ruby, sh/csh, TCL, Make, Perl - advantage This is a hybrid on-site position and will follow a 2+ day in-office work schedule, with in-office days based more »