Job Title: Digital Signal Processing (DSP) Engineer Location: Gloucester, UK Job Type: Permanent, Full-Time (37.5 hours per week - Four day working week ) Salary: £50,000 - £80,000 DOE Clearance: Due to the nature of the work, current DV or More ❯
advanced FPGAs and space-qualified ASICs. As an FPGA Engineer, you will: Translate complex signal processing algorithms into efficient RTL architectures Design and verify FPGA and ASIC IP using Verilog/SystemVerilog Validate and integrate designs on the latest FPGA development platforms Collaborate across architecture, verification, and physical implementation teams Contribute to UVM test environments and technical documentation Key skills … required for the FPGA Engineer: Strong RTL experience (Verilog/SystemVerilog) targeting FPGAs or ASICs Skilled in timing closure, synthesis, and power/resource optimisation Experience working on high-throughput digital signal processing blocks Familiarity with communications algorithms (e.g. FEC, beamforming) is a bonus Knowledge of UVM, scripting (Python), or AMBA protocols is desirable If you’re interested in the More ❯
portsmouth, hampshire, south east england, united kingdom
IC Resources
advanced FPGAs and space-qualified ASICs. As an FPGA Engineer, you will: Translate complex signal processing algorithms into efficient RTL architectures Design and verify FPGA and ASIC IP using Verilog/SystemVerilog Validate and integrate designs on the latest FPGA development platforms Collaborate across architecture, verification, and physical implementation teams Contribute to UVM test environments and technical documentation Key skills … required for the FPGA Engineer: Strong RTL experience (Verilog/SystemVerilog) targeting FPGAs or ASICs Skilled in timing closure, synthesis, and power/resource optimisation Experience working on high-throughput digital signal processing blocks Familiarity with communications algorithms (e.g. FEC, beamforming) is a bonus Knowledge of UVM, scripting (Python), or AMBA protocols is desirable If you’re interested in the More ❯
coverage etc. Qualifications: BS, MS in Electrical Engineering, Computer Engineering or Computer Science 8-20+ years and current hands-on experience in microarchitecture and RTL development Proficiency in Verilog, System Verilog Familiarity with industry-standard EDA tools and methodologies Experience with large high-speed, pipelined, stateful designs, and low power designs In-depth understanding of on-chip interconnects and More ❯
coverage etc. Qualifications: BS, MS in Electrical Engineering, Computer Engineering or Computer Science 8-20+ years and current hands-on experience in microarchitecture and RTL development Proficiency in Verilog, System Verilog Familiarity with industry-standard EDA tools and methodologies Experience with large high-speed, pipelined, stateful designs, and low power designs In-depth understanding of on-chip interconnects and More ❯
FPGA Engineer Location: Coventry Salary: £45,000-£50,000 We are excited to be supporting an established design consultancy who are looking to add an FPGA Engineer to their team. The role would offer the FPGA Engineer the opportunity to More ❯
FPGA Engineer Location: Coventry Salary: £45,000-£50,000 We are excited to be supporting an established design consultancy who are looking to add an FPGA Engineer to their team. The role would offer the FPGA Engineer the opportunity to More ❯
FPGA Engineer Location: Coventry Salary: £45,000-£50,000 We are excited to be supporting an established design consultancy who are looking to add an FPGA Engineer to their team. The role would offer the FPGA Engineer the opportunity to More ❯
Manchester, Lancashire, United Kingdom Hybrid / WFH Options
Arm Limited
automation and data analysis. "Nice To Have" Skills and Experience : Experience with SoC-level performance analysis and tools. Familiarity with memory subsystem micro-architecture and performance implications. Experience with Verilog/SystemVerilog RTL, including analysis and debugging in collaboration with design teams. Working knowledge of AMBA protocols and transaction-level modeling (SystemC/TLM). Exposure to Verilog/SystemVerilog More ❯
disciplinary team + Technical liaison, and maintenance and design specification of documentation Skills and Experience Required: + Deep understanding of FPGA fundamentals, fabric, and clocking resources + Proficiency in Verilog/System Verilog + Experience with RTL-level design + Previous telecommunications experience + Knowledge of 4G or 5G standards Bonus: + Experience with scripting languages (e.g. Python, Shell, Perl More ❯
Maidenhead, Royal Borough of Windsor and Maidenhead, Berkshire, United Kingdom
Platform Recruitment
disciplinary team + Technical liaison, and maintenance and design specification of documentation Skills and Experience Required: + Deep understanding of FPGA fundamentals, fabric, and clocking resources + Proficiency in Verilog/System Verilog + Experience with RTL-level design + Previous telecommunications experience + Knowledge of 4G or 5G standards Bonus: + Experience with scripting languages (e.g. Python, Shell, Perl More ❯
