Senior Design Verification Engineer
Oxfordshire, England, United Kingdom
Hybrid / WFH Options
Hybrid / WFH Options
IC Resources
PhD (desirable) 12+ years of digital ASIC verification experience Practical experience and understanding of: Requirement capture, verification planning and coverage closure System Verilog and UVM test benches Creation of UVM test benches System Verilog assertions Managing regression and debugging failures Scripting languages (e.g. Perl/Python/TCL) As this more ยป
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