26 to 50 of 53 Verilog Jobs in the South West

Essential Skills & Experience: Knowledge/Experience of developing/modelling/simulating software in at least one of the following areas: RF telecommunications, waveforms, OSI model, SIGINT, EW VHDL VERILOG Experience with SDR architecture Agile development methodologies. C#, C, C++, Python and Database architecture. Desirable Experience XML Networked systems JICD Restful and/or RPC API Library agnostic code development More ❯

Essential Skills & Experience: Knowledge/Experience of developing/modelling/simulating software in at least one of the following areas: RF telecommunications, waveforms, OSI model, SIGINT, EW VHDL VERILOG Experience with SDR architecture Agile development methodologies. C#, C, C++, Python and Database architecture. Desirable Experience XML Networked systems JICD Restful and/or RPC API Library agnostic code development More ❯

Essential Skills & Experience: Knowledge/Experience of developing/modelling/simulating software in at least one of the following areas: RF telecommunications, waveforms, OSI model, SIGINT, EW VHDL VERILOG Experience with SDR architecture Agile development methodologies. C#, C, C++, Python and Database architecture. Desirable Experience XML Networked systems JICD Restful and/or RPC API Library agnostic code development More ❯

Essential Skills & Experience: Knowledge/Experience of developing/modelling/simulating software in at least one of the following areas: RF telecommunications, waveforms, OSI model, SIGINT, EW VHDL VERILOG Experience with SDR architecture Agile development methodologies. C#, C, C++, Python and Database architecture. Desirable Experience XML Networked systems JICD Restful and/or RPC API Library agnostic code development More ❯

Essential Skills & Experience: Knowledge/Experience of developing/modelling/simulating software in at least one of the following areas: RF telecommunications, waveforms, OSI model, SIGINT, EW VHDL VERILOG Experience with SDR architecture Agile development methodologies. C#, C, C++, Python and Database architecture. Desirable Experience XML Networked systems JICD Restful and/or RPC API Library agnostic code development More ❯

/Scan/MBIST/BSD/LBIST/Boundary Scan insertion. ATPG/TC improvements and pattern generation. Pattern simulation (Zdel/SDF) and pattern verification (VCS, NC-Verilog, NC-Sim, ModelSim). Diagnosis of ATE failures and silicon bring-up. Deep understanding of DFT architecture design and implementation. Strong problem-solving skills and ability to lead or collaborate More ❯

Be responsible for defining, estimating and tracking of own work YOU SHOULD HAVE: Over 2 years recent and relevant module design experience within at least one HDL (VHDL/Verilog/SystemVerilog) Knowledge of computer systems and architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning tools (Git, SVN More ❯

Be responsible for defining, estimating and tracking of own work YOU SHOULD HAVE: Over 2 years recent and relevant module design experience within at least one HDL (VHDL/Verilog/SystemVerilog) Knowledge of computer systems and architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning tools (Git, SVN More ❯

Title: FPGA Design & Validation Engineer (Anywhere in UK or Europe)- 10+ Years Exp Xilinx, Verilog, Ethernet Location: Remote (anywhere in UK or Europe) Experience: 10+ Years We're hiring FPGA Design & Validation Engineers to work on high-performance systems in Industrial Automation and Ethernet-based Networking click apply for full job details More ❯

to but would best suit someone with 1-5 years of experience. Responsibilities Development of Wi-Fi products, including microcontrollers and connectivity. Test bench and test case generation using Verilog, SystemVerilog, UVM, C, Formal. Embedded C code or writing CPU-centric tests using C. Qualifications MSc in electrical engineering or equivalent or Bachelor with industrial experience. Knowledge of verification planning More ❯

chip interconnect protocols such as AMBA AHB, APB, and at least one variant of AXI, including AXI3, AXI4, AXI4-Lite, ACE, or AXI5 Proficient RTL design skills using VHDL, Verilog, or SystemVerilog Solid understanding of functional verification, ideally using SystemVerilog Demonstrated leadership in complex IP and full ASIC design projects from concept through to RTL completion. Knowledge of multiple chip More ❯

verification report as needed to show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases More ❯

verification report as needed to show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases More ❯

verification report as needed to show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases More ❯

deep understanding of all aspects of ASIC front-end design, from specification to RTL, and with a basic understanding of RTL to tape out flow. RTL Design - VHDL or Verilog Functional verification – ideally a good knowledge of System Verilog and the use of techniques such as assertions and coverage driven verification. SoC knowledge – including the selection and integration of 3rd More ❯

software,andRFengineeringteams Supportlabtesting,fieldtrials,andsystemvalidation WhatYouBring: ProvenexperiencewithDSPalgorithms,signalmodulation/demodulation,andRFanalysis ProficiencyinPython,C/C++,andDSPdevelopmenttools Hands-onknowledgeofSDRplatforms(e.g.GnuRadio) BackgroundinR&Dandreal-worldtestingofcomplexRFsystems Understandingofdigitalcommunicationprotocolsandsignalexploitationtechniques Candidatesmustbewillingandeligibletogothroughhighlevelsecurityclearancechecks DesirableSkills: ExperiencewithFPGAs(e.g.RFSoC),VHDL/Verilog FamiliaritywithLinux,GitLab,andcollaborativeDevOpsenvironments Priorworkindefence,intelligence,orcovertcommunicationssystems O.K.I'minwhat'snext? ApplywithyourlatestCVbelow More ❯

software,andRFengineeringteams Supportlabtesting,fieldtrials,andsystemvalidation WhatYouBring: ProvenexperiencewithDSPalgorithms,signalmodulation/demodulation,andRFanalysis ProficiencyinPython,C/C++,andDSPdevelopmenttools Hands-onknowledgeofSDRplatforms(e.g.GnuRadio) BackgroundinR&Dandreal-worldtestingofcomplexRFsystems Understandingofdigitalcommunicationprotocolsandsignalexploitationtechniques Candidatesmustbewillingandeligibletogothroughhighlevelsecurityclearancechecks DesirableSkills: ExperiencewithFPGAs(e.g.RFSoC),VHDL/Verilog FamiliaritywithLinux,GitLab,andcollaborativeDevOpsenvironments Priorworkindefence,intelligence,orcovertcommunicationssystems O.K.I'minwhat'snext? ApplywithyourlatestCVbelow JBRP1_UKTJ More ❯

on coverage analysis. Provide verification reports to demonstrate all tests passing on the RTL. Utilize methodologies including design checks, verification techniques with simulators and emulators such as UVM, formal, Verilog/SystemVerilog testbenches, and C, SystemVerilog, UVM test cases. #J-18808-Ljbffr More ❯

requirements based on analysis of coverage gaps. • Provide verification reports to demonstrate all tests passing on RTL. • Methodologies include design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM based test cases. #J-18808-Ljbffr More ❯

SDRAM, Wi-Fi, SDIO/eMMC, MIPI CSI/DSI Experience of interconnect standards ACE, AXI, AHB, and APB Ability to form requirements and specify architectural features. Expert-level Verilog/SystemVerilog for design and verification. Familiarity with scripting languages. The following would also be useful: The role is based on site in Cambridge with an expectation that you come More ❯

e.g. PhD, preferred) Extensive experience in block- and system-level IC design and verification, including technical leadership on successful design cycles. Proficiency in system-level modelling languages (e.g., VHDL, Verilog) Proficiency in scripting. As a top company, you can expect: Pension scheme, bonus structure, private healthcare. Flexible working arrangements (e.g., hybrid or remote work). Learning and development support. Wellbeing More ❯

Design, prototype, and verify advanced electronic circuits and systems Own schematic capture and PCB layout for digital, analog, and mixed-signal boards Develop embedded systems using FPGAs (VHDL/Verilog), microcontrollers, and SOCs What You’ll Bring Strong experience in schematic design and PCB layout Hands-on expertise in embedded C/Assembler for hardware interfacing Familiarity with PCIe, SPI More ❯

player Ability to work across teams and programming languages Desirable Experience in the technical specification of complex silicon SoC devices Experience of machine learning or massively parallel computing systems Verilog Low-level software experience Knowledge of one or more of DDR, PCIe, Ethernet, on-chip networks Benefits In addition to a competitive salary, Graphcore offers flexible working, a generous annual More ❯

by microarchitecture specification. · Implement power intent using customer’s flow · Trial synthesis and constraints updates, logical equivalency checking (LEC) Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC clock control · Synthesis using Design Compiler/Fusion compiler · RTL/gate level debug experience using tools More ❯

by microarchitecture specification. · Implement power intent using customer’s flow · Trial synthesis and constraints updates, logical equivalency checking (LEC) Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC clock control · Synthesis using Design Compiler/Fusion compiler · RTL/gate level debug experience using tools More ❯